Searched refs:DMA23 (Results 1 - 4 of 4) sorted by relevance

/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/
H A Dirq.h107 #define IRQ_MDMA1_SRC_CRC1 BFIN_IRQ(90) /* DMA23 Data (MDMA Stream 1 Source/CRC1 Input Channel) */
H A DdefBF60x_base.h2001 DMA23
2003 #define DMA23_NEXT_DESC_PTR 0xFFC09100 /* DMA23 Pointer to Next Initial Descriptor */
2004 #define DMA23_START_ADDR 0xFFC09104 /* DMA23 Start Address of Current Buffer */
2005 #define DMA23_CONFIG 0xFFC09108 /* DMA23 Configuration Register */
2006 #define DMA23_X_COUNT 0xFFC0910C /* DMA23 Inner Loop Count Start Value */
2007 #define DMA23_X_MODIFY 0xFFC09110 /* DMA23 Inner Loop Address Increment */
2008 #define DMA23_Y_COUNT 0xFFC09114 /* DMA23 Outer Loop Count Start Value (2D only) */
2009 #define DMA23_Y_MODIFY 0xFFC09118 /* DMA23 Outer Loop Address Increment (2D only) */
2010 #define DMA23_CURR_DESC_PTR 0xFFC09124 /* DMA23 Current Descriptor Pointer */
2011 #define DMA23_PREV_DESC_PTR 0xFFC09128 /* DMA23 Previous Initial Descriptor Pointer */
2012 #define DMA23_CURR_ADDR 0xFFC0912C /* DMA23 Current Address */
2013 #define DMA23_IRQ_STATUS 0xFFC09130 /* DMA23 Status Register */
2014 #define DMA23_CURR_X_COUNT 0xFFC09134 /* DMA23 Current Count(1D) or intra-row XCNT (2D) */
2015 #define DMA23_CURR_Y_COUNT 0xFFC09138 /* DMA23 Current Row Count (2D only) */
2016 #define DMA23_BWL_COUNT 0xFFC09140 /* DMA23 Bandwidth Limit Count */
2017 #define DMA23_CURR_BWL_COUNT 0xFFC09144 /* DMA23 Bandwidth Limit Count Current */
2018 #define DMA23_BWM_COUNT 0xFFC09148 /* DMA23 Bandwidth Monitor Count */
2019 #define DMA23_CURR_BWM_COUNT 0xFFC0914C /* DMA23 Bandwidth Monitor Count Current */
/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
H A Dirq.h54 #define IRQ_SPI2 BFIN_IRQ(40) /* SPI2 (DMA23) Interrupt */
H A DdefBF54x_base.h1556 #define DMA23 0x100 /* DMA Channel 23 */ macro

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