Searched refs:DMA21 (Results 1 - 5 of 5) sorted by relevance

/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
H A Ddma.h58 #define IRQ_UART3_TX BFIN_IRQ(36) /* UART3 TX (DMA21) Interrupt */
H A Dirq.h50 #define IRQ_SPORT3_TX BFIN_IRQ(36) /* SPORT3 TX (DMA21) Interrupt */
H A DdefBF54x_base.h1552 #define DMA21 0x10 /* DMA Channel 21 */ macro
/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/
H A Dirq.h102 #define IRQ_MDMA0_SRC_CRC0 BFIN_IRQ(86) /* DMA21 Data (MDMA Stream 0 Source/CRC0 Input Channel) */
H A DdefBF60x_base.h1959 DMA21
1961 #define DMA21_NEXT_DESC_PTR 0xFFC09000 /* DMA21 Pointer to Next Initial Descriptor */
1962 #define DMA21_START_ADDR 0xFFC09004 /* DMA21 Start Address of Current Buffer */
1963 #define DMA21_CONFIG 0xFFC09008 /* DMA21 Configuration Register */
1964 #define DMA21_X_COUNT 0xFFC0900C /* DMA21 Inner Loop Count Start Value */
1965 #define DMA21_X_MODIFY 0xFFC09010 /* DMA21 Inner Loop Address Increment */
1966 #define DMA21_Y_COUNT 0xFFC09014 /* DMA21 Outer Loop Count Start Value (2D only) */
1967 #define DMA21_Y_MODIFY 0xFFC09018 /* DMA21 Outer Loop Address Increment (2D only) */
1968 #define DMA21_CURR_DESC_PTR 0xFFC09024 /* DMA21 Current Descriptor Pointer */
1969 #define DMA21_PREV_DESC_PTR 0xFFC09028 /* DMA21 Previous Initial Descriptor Pointer */
1970 #define DMA21_CURR_ADDR 0xFFC0902C /* DMA21 Current Address */
1971 #define DMA21_IRQ_STATUS 0xFFC09030 /* DMA21 Status Register */
1972 #define DMA21_CURR_X_COUNT 0xFFC09034 /* DMA21 Current Count(1D) or intra-row XCNT (2D) */
1973 #define DMA21_CURR_Y_COUNT 0xFFC09038 /* DMA21 Current Row Count (2D only) */
1974 #define DMA21_BWL_COUNT 0xFFC09040 /* DMA21 Bandwidth Limit Count */
1975 #define DMA21_CURR_BWL_COUNT 0xFFC09044 /* DMA21 Bandwidth Limit Count Current */
1976 #define DMA21_BWM_COUNT 0xFFC09048 /* DMA21 Bandwidth Monitor Count */
1977 #define DMA21_CURR_BWM_COUNT 0xFFC0904C /* DMA21 Bandwidth Monitor Count Current */

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