Searched refs:DMA20 (Results 1 - 5 of 5) sorted by relevance

/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
H A Ddma.h56 #define IRQ_UART3_RX BFIN_IRQ(35) /* UART3 RX (DMA20) Interrupt */
H A Dirq.h49 #define IRQ_SPORT3_RX BFIN_IRQ(35) /* SPORT3 RX (DMA20) Interrupt */
H A DdefBF54x_base.h1551 #define DMA20 0x8 /* DMA Channel 20 */ macro
/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/
H A Dirq.h100 #define IRQ_UART1_RX BFIN_IRQ(84) /* UART1 RX Interrupt (DMA20) */
H A DdefBF60x_base.h1938 DMA20
1940 #define DMA20_NEXT_DESC_PTR 0xFFC07380 /* DMA20 Pointer to Next Initial Descriptor */
1941 #define DMA20_START_ADDR 0xFFC07384 /* DMA20 Start Address of Current Buffer */
1942 #define DMA20_CONFIG 0xFFC07388 /* DMA20 Configuration Register */
1943 #define DMA20_X_COUNT 0xFFC0738C /* DMA20 Inner Loop Count Start Value */
1944 #define DMA20_X_MODIFY 0xFFC07390 /* DMA20 Inner Loop Address Increment */
1945 #define DMA20_Y_COUNT 0xFFC07394 /* DMA20 Outer Loop Count Start Value (2D only) */
1946 #define DMA20_Y_MODIFY 0xFFC07398 /* DMA20 Outer Loop Address Increment (2D only) */
1947 #define DMA20_CURR_DESC_PTR 0xFFC073A4 /* DMA20 Current Descriptor Pointer */
1948 #define DMA20_PREV_DESC_PTR 0xFFC073A8 /* DMA20 Previous Initial Descriptor Pointer */
1949 #define DMA20_CURR_ADDR 0xFFC073AC /* DMA20 Current Address */
1950 #define DMA20_IRQ_STATUS 0xFFC073B0 /* DMA20 Status Register */
1951 #define DMA20_CURR_X_COUNT 0xFFC073B4 /* DMA20 Current Count(1D) or intra-row XCNT (2D) */
1952 #define DMA20_CURR_Y_COUNT 0xFFC073B8 /* DMA20 Current Row Count (2D only) */
1953 #define DMA20_BWL_COUNT 0xFFC073C0 /* DMA20 Bandwidth Limit Count */
1954 #define DMA20_CURR_BWL_COUNT 0xFFC073C4 /* DMA20 Bandwidth Limit Count Current */
1955 #define DMA20_BWM_COUNT 0xFFC073C8 /* DMA20 Bandwidth Monitor Count */
1956 #define DMA20_CURR_BWM_COUNT 0xFFC073CC /* DMA20 Bandwidth Monitor Count Current */

Completed in 214 milliseconds