/linux-4.4.14/arch/blackfin/mach-bf561/include/mach/ |
H A D | irq.h | 17 #define IRQ_DMA2_ERROR BFIN_IRQ(2) /* DMA2 Error (general) */ 42 #define IRQ_DMA2_0 BFIN_IRQ(23) /* DMA2 0 (SPORT0 RX) */ 43 #define IRQ_SPORT0_RX IRQ_DMA2_0 /* DMA2 0 (SPORT0 RX) */ 44 #define IRQ_DMA2_1 BFIN_IRQ(24) /* DMA2 1 (SPORT0 TX) */ 45 #define IRQ_SPORT0_TX IRQ_DMA2_1 /* DMA2 1 (SPORT0 TX) */ 46 #define IRQ_DMA2_2 BFIN_IRQ(25) /* DMA2 2 (SPORT1 RX) */ 47 #define IRQ_SPORT1_RX IRQ_DMA2_2 /* DMA2 2 (SPORT1 RX) */ 48 #define IRQ_DMA2_3 BFIN_IRQ(26) /* DMA2 3 (SPORT2 TX) */ 49 #define IRQ_SPORT1_TX IRQ_DMA2_3 /* DMA2 3 (SPORT2 TX) */ 50 #define IRQ_DMA2_4 BFIN_IRQ(27) /* DMA2 4 (SPI) */ 51 #define IRQ_SPI IRQ_DMA2_4 /* DMA2 4 (SPI) */ 52 #define IRQ_DMA2_5 BFIN_IRQ(28) /* DMA2 5 (UART RX) */ 53 #define IRQ_UART_RX IRQ_DMA2_5 /* DMA2 5 (UART RX) */ 54 #define IRQ_DMA2_6 BFIN_IRQ(29) /* DMA2 6 (UART TX) */ 55 #define IRQ_UART_TX IRQ_DMA2_6 /* DMA2 6 (UART TX) */ 56 #define IRQ_DMA2_7 BFIN_IRQ(30) /* DMA2 7 Interrupt */ 57 #define IRQ_DMA2_8 BFIN_IRQ(31) /* DMA2 8 Interrupt */ 58 #define IRQ_DMA2_9 BFIN_IRQ(32) /* DMA2 9 Interrupt */ 59 #define IRQ_DMA2_10 BFIN_IRQ(33) /* DMA2 10 Interrupt */ 60 #define IRQ_DMA2_11 BFIN_IRQ(34) /* DMA2 11 Interrupt */
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H A D | defBF561.h | 538 /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ 539 #define DMA2_0_CONFIG 0xFFC00C08 /* DMA2 Channel 0 Configuration register */ 540 #define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */ 541 #define DMA2_0_START_ADDR 0xFFC00C04 /* DMA2 Channel 0 Start Address */ 542 #define DMA2_0_X_COUNT 0xFFC00C10 /* DMA2 Channel 0 Inner Loop Count */ 543 #define DMA2_0_Y_COUNT 0xFFC00C18 /* DMA2 Channel 0 Outer Loop Count */ 544 #define DMA2_0_X_MODIFY 0xFFC00C14 /* DMA2 Channel 0 Inner Loop Addr Increment */ 545 #define DMA2_0_Y_MODIFY 0xFFC00C1C /* DMA2 Channel 0 Outer Loop Addr Increment */ 546 #define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */ 547 #define DMA2_0_CURR_ADDR 0xFFC00C24 /* DMA2 Channel 0 Current Address Pointer */ 548 #define DMA2_0_CURR_X_COUNT 0xFFC00C30 /* DMA2 Channel 0 Current Inner Loop Count */ 549 #define DMA2_0_CURR_Y_COUNT 0xFFC00C38 /* DMA2 Channel 0 Current Outer Loop Count */ 550 #define DMA2_0_IRQ_STATUS 0xFFC00C28 /* DMA2 Channel 0 Interrupt/Status Register */ 551 #define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C /* DMA2 Channel 0 Peripheral Map Register */ 553 #define DMA2_1_CONFIG 0xFFC00C48 /* DMA2 Channel 1 Configuration register */ 554 #define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */ 555 #define DMA2_1_START_ADDR 0xFFC00C44 /* DMA2 Channel 1 Start Address */ 556 #define DMA2_1_X_COUNT 0xFFC00C50 /* DMA2 Channel 1 Inner Loop Count */ 557 #define DMA2_1_Y_COUNT 0xFFC00C58 /* DMA2 Channel 1 Outer Loop Count */ 558 #define DMA2_1_X_MODIFY 0xFFC00C54 /* DMA2 Channel 1 Inner Loop Addr Increment */ 559 #define DMA2_1_Y_MODIFY 0xFFC00C5C /* DMA2 Channel 1 Outer Loop Addr Increment */ 560 #define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */ 561 #define DMA2_1_CURR_ADDR 0xFFC00C64 /* DMA2 Channel 1 Current Address Pointer */ 562 #define DMA2_1_CURR_X_COUNT 0xFFC00C70 /* DMA2 Channel 1 Current Inner Loop Count */ 563 #define DMA2_1_CURR_Y_COUNT 0xFFC00C78 /* DMA2 Channel 1 Current Outer Loop Count */ 564 #define DMA2_1_IRQ_STATUS 0xFFC00C68 /* DMA2 Channel 1 Interrupt/Status Register */ 565 #define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C /* DMA2 Channel 1 Peripheral Map Register */ 567 #define DMA2_2_CONFIG 0xFFC00C88 /* DMA2 Channel 2 Configuration register */ 568 #define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */ 569 #define DMA2_2_START_ADDR 0xFFC00C84 /* DMA2 Channel 2 Start Address */ 570 #define DMA2_2_X_COUNT 0xFFC00C90 /* DMA2 Channel 2 Inner Loop Count */ 571 #define DMA2_2_Y_COUNT 0xFFC00C98 /* DMA2 Channel 2 Outer Loop Count */ 572 #define DMA2_2_X_MODIFY 0xFFC00C94 /* DMA2 Channel 2 Inner Loop Addr Increment */ 573 #define DMA2_2_Y_MODIFY 0xFFC00C9C /* DMA2 Channel 2 Outer Loop Addr Increment */ 574 #define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */ 575 #define DMA2_2_CURR_ADDR 0xFFC00CA4 /* DMA2 Channel 2 Current Address Pointer */ 576 #define DMA2_2_CURR_X_COUNT 0xFFC00CB0 /* DMA2 Channel 2 Current Inner Loop Count */ 577 #define DMA2_2_CURR_Y_COUNT 0xFFC00CB8 /* DMA2 Channel 2 Current Outer Loop Count */ 578 #define DMA2_2_IRQ_STATUS 0xFFC00CA8 /* DMA2 Channel 2 Interrupt/Status Register */ 579 #define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC /* DMA2 Channel 2 Peripheral Map Register */ 581 #define DMA2_3_CONFIG 0xFFC00CC8 /* DMA2 Channel 3 Configuration register */ 582 #define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */ 583 #define DMA2_3_START_ADDR 0xFFC00CC4 /* DMA2 Channel 3 Start Address */ 584 #define DMA2_3_X_COUNT 0xFFC00CD0 /* DMA2 Channel 3 Inner Loop Count */ 585 #define DMA2_3_Y_COUNT 0xFFC00CD8 /* DMA2 Channel 3 Outer Loop Count */ 586 #define DMA2_3_X_MODIFY 0xFFC00CD4 /* DMA2 Channel 3 Inner Loop Addr Increment */ 587 #define DMA2_3_Y_MODIFY 0xFFC00CDC /* DMA2 Channel 3 Outer Loop Addr Increment */ 588 #define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */ 589 #define DMA2_3_CURR_ADDR 0xFFC00CE4 /* DMA2 Channel 3 Current Address Pointer */ 590 #define DMA2_3_CURR_X_COUNT 0xFFC00CF0 /* DMA2 Channel 3 Current Inner Loop Count */ 591 #define DMA2_3_CURR_Y_COUNT 0xFFC00CF8 /* DMA2 Channel 3 Current Outer Loop Count */ 592 #define DMA2_3_IRQ_STATUS 0xFFC00CE8 /* DMA2 Channel 3 Interrupt/Status Register */ 593 #define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC /* DMA2 Channel 3 Peripheral Map Register */ 595 #define DMA2_4_CONFIG 0xFFC00D08 /* DMA2 Channel 4 Configuration register */ 596 #define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */ 597 #define DMA2_4_START_ADDR 0xFFC00D04 /* DMA2 Channel 4 Start Address */ 598 #define DMA2_4_X_COUNT 0xFFC00D10 /* DMA2 Channel 4 Inner Loop Count */ 599 #define DMA2_4_Y_COUNT 0xFFC00D18 /* DMA2 Channel 4 Outer Loop Count */ 600 #define DMA2_4_X_MODIFY 0xFFC00D14 /* DMA2 Channel 4 Inner Loop Addr Increment */ 601 #define DMA2_4_Y_MODIFY 0xFFC00D1C /* DMA2 Channel 4 Outer Loop Addr Increment */ 602 #define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */ 603 #define DMA2_4_CURR_ADDR 0xFFC00D24 /* DMA2 Channel 4 Current Address Pointer */ 604 #define DMA2_4_CURR_X_COUNT 0xFFC00D30 /* DMA2 Channel 4 Current Inner Loop Count */ 605 #define DMA2_4_CURR_Y_COUNT 0xFFC00D38 /* DMA2 Channel 4 Current Outer Loop Count */ 606 #define DMA2_4_IRQ_STATUS 0xFFC00D28 /* DMA2 Channel 4 Interrupt/Status Register */ 607 #define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C /* DMA2 Channel 4 Peripheral Map Register */ 609 #define DMA2_5_CONFIG 0xFFC00D48 /* DMA2 Channel 5 Configuration register */ 610 #define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */ 611 #define DMA2_5_START_ADDR 0xFFC00D44 /* DMA2 Channel 5 Start Address */ 612 #define DMA2_5_X_COUNT 0xFFC00D50 /* DMA2 Channel 5 Inner Loop Count */ 613 #define DMA2_5_Y_COUNT 0xFFC00D58 /* DMA2 Channel 5 Outer Loop Count */ 614 #define DMA2_5_X_MODIFY 0xFFC00D54 /* DMA2 Channel 5 Inner Loop Addr Increment */ 615 #define DMA2_5_Y_MODIFY 0xFFC00D5C /* DMA2 Channel 5 Outer Loop Addr Increment */ 616 #define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */ 617 #define DMA2_5_CURR_ADDR 0xFFC00D64 /* DMA2 Channel 5 Current Address Pointer */ 618 #define DMA2_5_CURR_X_COUNT 0xFFC00D70 /* DMA2 Channel 5 Current Inner Loop Count */ 619 #define DMA2_5_CURR_Y_COUNT 0xFFC00D78 /* DMA2 Channel 5 Current Outer Loop Count */ 620 #define DMA2_5_IRQ_STATUS 0xFFC00D68 /* DMA2 Channel 5 Interrupt/Status Register */ 621 #define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C /* DMA2 Channel 5 Peripheral Map Register */ 623 #define DMA2_6_CONFIG 0xFFC00D88 /* DMA2 Channel 6 Configuration register */ 624 #define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */ 625 #define DMA2_6_START_ADDR 0xFFC00D84 /* DMA2 Channel 6 Start Address */ 626 #define DMA2_6_X_COUNT 0xFFC00D90 /* DMA2 Channel 6 Inner Loop Count */ 627 #define DMA2_6_Y_COUNT 0xFFC00D98 /* DMA2 Channel 6 Outer Loop Count */ 628 #define DMA2_6_X_MODIFY 0xFFC00D94 /* DMA2 Channel 6 Inner Loop Addr Increment */ 629 #define DMA2_6_Y_MODIFY 0xFFC00D9C /* DMA2 Channel 6 Outer Loop Addr Increment */ 630 #define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */ 631 #define DMA2_6_CURR_ADDR 0xFFC00DA4 /* DMA2 Channel 6 Current Address Pointer */ 632 #define DMA2_6_CURR_X_COUNT 0xFFC00DB0 /* DMA2 Channel 6 Current Inner Loop Count */ 633 #define DMA2_6_CURR_Y_COUNT 0xFFC00DB8 /* DMA2 Channel 6 Current Outer Loop Count */ 634 #define DMA2_6_IRQ_STATUS 0xFFC00DA8 /* DMA2 Channel 6 Interrupt/Status Register */ 635 #define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC /* DMA2 Channel 6 Peripheral Map Register */ 637 #define DMA2_7_CONFIG 0xFFC00DC8 /* DMA2 Channel 7 Configuration register */ 638 #define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */ 639 #define DMA2_7_START_ADDR 0xFFC00DC4 /* DMA2 Channel 7 Start Address */ 640 #define DMA2_7_X_COUNT 0xFFC00DD0 /* DMA2 Channel 7 Inner Loop Count */ 641 #define DMA2_7_Y_COUNT 0xFFC00DD8 /* DMA2 Channel 7 Outer Loop Count */ 642 #define DMA2_7_X_MODIFY 0xFFC00DD4 /* DMA2 Channel 7 Inner Loop Addr Increment */ 643 #define DMA2_7_Y_MODIFY 0xFFC00DDC /* DMA2 Channel 7 Outer Loop Addr Increment */ 644 #define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */ 645 #define DMA2_7_CURR_ADDR 0xFFC00DE4 /* DMA2 Channel 7 Current Address Pointer */ 646 #define DMA2_7_CURR_X_COUNT 0xFFC00DF0 /* DMA2 Channel 7 Current Inner Loop Count */ 647 #define DMA2_7_CURR_Y_COUNT 0xFFC00DF8 /* DMA2 Channel 7 Current Outer Loop Count */ 648 #define DMA2_7_IRQ_STATUS 0xFFC00DE8 /* DMA2 Channel 7 Interrupt/Status Register */ 649 #define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC /* DMA2 Channel 7 Peripheral Map Register */ 651 #define DMA2_8_CONFIG 0xFFC00E08 /* DMA2 Channel 8 Configuration register */ 652 #define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */ 653 #define DMA2_8_START_ADDR 0xFFC00E04 /* DMA2 Channel 8 Start Address */ 654 #define DMA2_8_X_COUNT 0xFFC00E10 /* DMA2 Channel 8 Inner Loop Count */ 655 #define DMA2_8_Y_COUNT 0xFFC00E18 /* DMA2 Channel 8 Outer Loop Count */ 656 #define DMA2_8_X_MODIFY 0xFFC00E14 /* DMA2 Channel 8 Inner Loop Addr Increment */ 657 #define DMA2_8_Y_MODIFY 0xFFC00E1C /* DMA2 Channel 8 Outer Loop Addr Increment */ 658 #define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */ 659 #define DMA2_8_CURR_ADDR 0xFFC00E24 /* DMA2 Channel 8 Current Address Pointer */ 660 #define DMA2_8_CURR_X_COUNT 0xFFC00E30 /* DMA2 Channel 8 Current Inner Loop Count */ 661 #define DMA2_8_CURR_Y_COUNT 0xFFC00E38 /* DMA2 Channel 8 Current Outer Loop Count */ 662 #define DMA2_8_IRQ_STATUS 0xFFC00E28 /* DMA2 Channel 8 Interrupt/Status Register */ 663 #define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C /* DMA2 Channel 8 Peripheral Map Register */ 665 #define DMA2_9_CONFIG 0xFFC00E48 /* DMA2 Channel 9 Configuration register */ 666 #define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */ 667 #define DMA2_9_START_ADDR 0xFFC00E44 /* DMA2 Channel 9 Start Address */ 668 #define DMA2_9_X_COUNT 0xFFC00E50 /* DMA2 Channel 9 Inner Loop Count */ 669 #define DMA2_9_Y_COUNT 0xFFC00E58 /* DMA2 Channel 9 Outer Loop Count */ 670 #define DMA2_9_X_MODIFY 0xFFC00E54 /* DMA2 Channel 9 Inner Loop Addr Increment */ 671 #define DMA2_9_Y_MODIFY 0xFFC00E5C /* DMA2 Channel 9 Outer Loop Addr Increment */ 672 #define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */ 673 #define DMA2_9_CURR_ADDR 0xFFC00E64 /* DMA2 Channel 9 Current Address Pointer */ 674 #define DMA2_9_CURR_X_COUNT 0xFFC00E70 /* DMA2 Channel 9 Current Inner Loop Count */ 675 #define DMA2_9_CURR_Y_COUNT 0xFFC00E78 /* DMA2 Channel 9 Current Outer Loop Count */ 676 #define DMA2_9_IRQ_STATUS 0xFFC00E68 /* DMA2 Channel 9 Interrupt/Status Register */ 677 #define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C /* DMA2 Channel 9 Peripheral Map Register */ 679 #define DMA2_10_CONFIG 0xFFC00E88 /* DMA2 Channel 10 Configuration register */ 680 #define DMA2_10_NEXT_DESC_PTR 0xFFC00E80 /* DMA2 Channel 10 Next Descripter Ptr Reg */ 681 #define DMA2_10_START_ADDR 0xFFC00E84 /* DMA2 Channel 10 Start Address */ 682 #define DMA2_10_X_COUNT 0xFFC00E90 /* DMA2 Channel 10 Inner Loop Count */ 683 #define DMA2_10_Y_COUNT 0xFFC00E98 /* DMA2 Channel 10 Outer Loop Count */ 684 #define DMA2_10_X_MODIFY 0xFFC00E94 /* DMA2 Channel 10 Inner Loop Addr Increment */ 685 #define DMA2_10_Y_MODIFY 0xFFC00E9C /* DMA2 Channel 10 Outer Loop Addr Increment */ 686 #define DMA2_10_CURR_DESC_PTR 0xFFC00EA0 /* DMA2 Channel 10 Current Descriptor Pointer */ 687 #define DMA2_10_CURR_ADDR 0xFFC00EA4 /* DMA2 Channel 10 Current Address Pointer */ 688 #define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */ 689 #define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */ 690 #define DMA2_10_IRQ_STATUS 0xFFC00EA8 /* DMA2 Channel 10 Interrupt/Status Register */ 691 #define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC /* DMA2 Channel 10 Peripheral Map Register */ 693 #define DMA2_11_CONFIG 0xFFC00EC8 /* DMA2 Channel 11 Configuration register */ 694 #define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0 /* DMA2 Channel 11 Next Descripter Ptr Reg */ 695 #define DMA2_11_START_ADDR 0xFFC00EC4 /* DMA2 Channel 11 Start Address */ 696 #define DMA2_11_X_COUNT 0xFFC00ED0 /* DMA2 Channel 11 Inner Loop Count */ 697 #define DMA2_11_Y_COUNT 0xFFC00ED8 /* DMA2 Channel 11 Outer Loop Count */ 698 #define DMA2_11_X_MODIFY 0xFFC00ED4 /* DMA2 Channel 11 Inner Loop Addr Increment */ 699 #define DMA2_11_Y_MODIFY 0xFFC00EDC /* DMA2 Channel 11 Outer Loop Addr Increment */ 700 #define DMA2_11_CURR_DESC_PTR 0xFFC00EE0 /* DMA2 Channel 11 Current Descriptor Pointer */ 701 #define DMA2_11_CURR_ADDR 0xFFC00EE4 /* DMA2 Channel 11 Current Address Pointer */ 702 #define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */ 703 #define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */ 704 #define DMA2_11_IRQ_STATUS 0xFFC00EE8 /* DMA2 Channel 11 Interrupt/Status Register */ 705 #define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC /* DMA2 Channel 11 Peripheral Map Register */ 707 /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
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H A D | cdefBF561.h | 944 /* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */ 1257 /* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
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/linux-4.4.14/arch/blackfin/mach-bf538/include/mach/ |
H A D | defBF539.h | 73 #define MXVR_DMA2_CONFIG 0xFFC027C0 /* MXVR Sync Data DMA2 Config Register */ 74 #define MXVR_DMA2_START_ADDR 0xFFC027C4 /* MXVR Sync Data DMA2 Start Address Register */ 75 #define MXVR_DMA2_COUNT 0xFFC027C8 /* MXVR Sync Data DMA2 Loop Count Register */ 76 #define MXVR_DMA2_CURR_ADDR 0xFFC027CC /* MXVR Sync Data DMA2 Current Address Register */ 77 #define MXVR_DMA2_CURR_COUNT 0xFFC027D0 /* MXVR Sync Data DMA2 Current Loop Count Register */
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/linux-4.4.14/arch/sh/drivers/pci/ |
H A D | pci-sh4.h | 60 #define SH4_PCICLR_MDMA2 0x10000000 /* DMA2 Transfer Error */ 99 #define SH4_PCIDPA2 0x1A0 /* DMA2 Transfer Addr. */ 100 #define SH4_PCIDLA2 0x1A4 /* DMA2 Local Addr. */ 101 #define SH4_PCIDTC2 0x1A8 /* DMA2 Transfer Cnt. */ 102 #define SH4_PCIDCR2 0x1AC /* DMA2 Control Register */
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/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/ |
H A D | defBF549.h | 78 /* MXVR DMA2 Registers */ 80 #define MXVR_DMA2_CONFIG 0xffc027c0 /* MXVR Sync Data DMA2 Config Register */ 81 #define MXVR_DMA2_START_ADDR 0xffc027c4 /* MXVR Sync Data DMA2 Start Address */ 82 #define MXVR_DMA2_COUNT 0xffc027c8 /* MXVR Sync Data DMA2 Loop Count Register */ 83 #define MXVR_DMA2_CURR_ADDR 0xffc027cc /* MXVR Sync Data DMA2 Current Address */ 84 #define MXVR_DMA2_CURR_COUNT 0xffc027d0 /* MXVR Sync Data DMA2 Current Loop Count */
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H A D | cdefBF549.h | 125 /* MXVR DMA2 Registers */
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H A D | irq.h | 25 #define IRQ_SPORT1_RX BFIN_IRQ(11) /* SPORT1 RX Interrupt (DMA2) */
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H A D | defBF542.h | 725 #define DMA2_INT 0x4 /* DMA2 pending interrupt */
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H A D | defBF547.h | 1002 #define DMA2_INT 0x4 /* DMA2 pending interrupt */
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H A D | defBF54x_base.h | 1527 #define DMA2 0x800 /* DMA Channel 2 */ macro
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/linux-4.4.14/drivers/media/pci/b2c2/ |
H A D | flexcop-dma.c | 60 err("either DMA1 or DMA2 can be configured within one " flexcop_dma_config() 85 err("either transfer DMA1 or DMA2 can be started within one " flexcop_dma_xfer_control()
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/linux-4.4.14/arch/blackfin/mach-bf537/include/mach/ |
H A D | irq.h | 32 #define IRQ_PH_INTB_MAC_TX BFIN_IRQ(18) /* Port H Interrupt B & DMA2 Interrupt (Ethernet TX) */ 124 #define IRQ_MAC_TX 108 /* DMA2 Interrupt (Ethernet TX) */
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/linux-4.4.14/arch/blackfin/mach-bf527/include/mach/ |
H A D | irq.h | 42 #define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */ 43 #define IRQ_NFC BFIN_IRQ(30) /* DMA2 Channel (MAC TX/NAND) */
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H A D | defBF525.h | 635 #define DMA2_INT 0x4 /* DMA2 pending interrupt */
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/linux-4.4.14/arch/sparc/include/asm/ |
H A D | sunbpp.h | 13 __volatile__ __u32 p_tst_csr; /* Test Control/Status (DMA2 only) */
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/linux-4.4.14/arch/blackfin/mach-bf533/include/mach/ |
H A D | irq.h | 24 #define IRQ_SPORT0_TX BFIN_IRQ(10) /* DMA2 Interrupt (SPORT0 TX) */
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/linux-4.4.14/arch/powerpc/include/asm/ |
H A D | tsi108_irq.h | 66 #define IRQ_TSI108_DMA2 TSI108_IRQ(10) /* DMA2 */
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H A D | cpm1.h | 326 ushort sen_maxd2; /* maximum DMA2 length */
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H A D | cpm2.h | 348 ushort sen_maxd2; /* maximum DMA2 length */ 579 ushort fen_maxd2; /* Max DMA2 length (1520) */
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/linux-4.4.14/arch/mips/loongson32/common/ |
H A D | irq.c | 127 /* set DMA0, DMA1 and DMA2 to edge trigger */ ls1x_irq_init()
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/linux-4.4.14/arch/mips/txx9/rbtx4938/ |
H A D | irq.c | 35 * TXX9_IRQ_BASE+12 TX4938 DMA2
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/linux-4.4.14/sound/isa/ |
H A D | cmi8328.c | 61 MODULE_PARM_DESC(dma2, "DMA2 for CMI8328 driver."); 267 snd_printk(KERN_WARNING "unable to find a free DMA2, full-duplex will not work\n"); snd_cmi8328_probe() 285 /* ...and DMA2 */ snd_cmi8328_probe() 289 snd_printk(KERN_ERR "invalid DMA2 %d\n", dma2[ndev]); snd_cmi8328_probe()
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H A D | sscape.c | 82 MODULE_PARM_DESC(dma2, "DMA2 # for SoundScape driver."); 1081 "%s at 0x%lx, IRQ %d, DMA1 %d, DMA2 %d\n", create_sscape()
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H A D | es18xx.c | 110 int dma2; /* DMA2 */ 1826 snd_printk(KERN_ERR PFX "unable to grap DMA2 %d\n", dma2); snd_es18xx_new_device() 2224 snd_printk(KERN_ERR PFX "unable to find a free DMA2\n"); snd_es18xx_isa_probe()
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H A D | opl3sa2.c | 87 MODULE_PARM_DESC(dma2, "DMA2 # for OPL3-SA driver.");
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/linux-4.4.14/sound/isa/gus/ |
H A D | gusclassic.c | 68 MODULE_PARM_DESC(dma2, "DMA2 # for " CRD_NAME " driver."); 108 dev_err(dev, "unable to find a free DMA2\n"); snd_gusclassic_create()
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H A D | gusmax.c | 66 MODULE_PARM_DESC(dma2, "DMA2 # for GUS MAX driver."); 245 snd_printk(KERN_ERR PFX "unable to find a free DMA2\n"); snd_gusmax_probe()
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H A D | gus_main.c | 198 snd_printk(KERN_ERR "gus: can't grab DMA2 %d\n", dma2); snd_gus_create()
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H A D | interwave.c | 106 MODULE_PARM_DESC(dma2, "DMA2 # for InterWave driver."); 822 snd_printk(KERN_ERR PFX "unable to find a free DMA2\n"); snd_interwave_isa_probe()
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/linux-4.4.14/arch/blackfin/mach-bf518/include/mach/ |
H A D | irq.h | 45 #define IRQ_MAC_TX BFIN_IRQ(30) /* DMA2 Channel (MAC TX) */
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/linux-4.4.14/sound/isa/cs423x/ |
H A D | cs4231.c | 69 MODULE_PARM_DESC(dma2, "DMA2 # for " CRD_NAME " driver.");
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H A D | cs4236.c | 118 MODULE_PARM_DESC(dma2, "DMA2 # for " IDENT " driver.");
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/linux-4.4.14/drivers/acpi/acpica/ |
H A D | hwvalid.c | 75 * DMA2: DMA 2 page registers 94 {"DMA2", 0x0089, 0x008B, ACPI_OSI_WIN_XP},
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/linux-4.4.14/drivers/irqchip/ |
H A D | irq-s3c24xx.c | 656 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ 725 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ 863 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */ 930 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ 1005 { .type = S3C_IRQTYPE_EDGE, }, /* DMA2 */ 1115 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 17 }, /* DMA2 */
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/linux-4.4.14/drivers/net/wireless/ath/wcn36xx/ |
H A D | dxe.h | 27 H2H_TEST_RX_TX = DMA2
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/linux-4.4.14/drivers/net/irda/ |
H A D | via-ircc.h | 173 #define DMA2 0xc0 macro 175 #define MASK2 DMA2+0x14
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/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/ |
H A D | irq.h | 63 #define IRQ_SPORT1_TX BFIN_IRQ(47) /* SPORT1 TX Interrupt (DMA2) */
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H A D | defBF60x_base.h | 1560 DMA2 1562 #define DMA2_NEXT_DESC_PTR 0xFFC41100 /* DMA2 Pointer to Next Initial Descriptor */ 1563 #define DMA2_START_ADDR 0xFFC41104 /* DMA2 Start Address of Current Buffer */ 1564 #define DMA2_CONFIG 0xFFC41108 /* DMA2 Configuration Register */ 1565 #define DMA2_X_COUNT 0xFFC4110C /* DMA2 Inner Loop Count Start Value */ 1566 #define DMA2_X_MODIFY 0xFFC41110 /* DMA2 Inner Loop Address Increment */ 1567 #define DMA2_Y_COUNT 0xFFC41114 /* DMA2 Outer Loop Count Start Value (2D only) */ 1568 #define DMA2_Y_MODIFY 0xFFC41118 /* DMA2 Outer Loop Address Increment (2D only) */ 1569 #define DMA2_CURR_DESC_PTR 0xFFC41124 /* DMA2 Current Descriptor Pointer */ 1570 #define DMA2_PREV_DESC_PTR 0xFFC41128 /* DMA2 Previous Initial Descriptor Pointer */ 1571 #define DMA2_CURR_ADDR 0xFFC4112C /* DMA2 Current Address */ 1572 #define DMA2_IRQ_STATUS 0xFFC41130 /* DMA2 Status Register */ 1573 #define DMA2_CURR_X_COUNT 0xFFC41134 /* DMA2 Current Count(1D) or intra-row XCNT (2D) */ 1574 #define DMA2_CURR_Y_COUNT 0xFFC41138 /* DMA2 Current Row Count (2D only) */ 1575 #define DMA2_BWL_COUNT 0xFFC41140 /* DMA2 Bandwidth Limit Count */ 1576 #define DMA2_CURR_BWL_COUNT 0xFFC41144 /* DMA2 Bandwidth Limit Count Current */ 1577 #define DMA2_BWM_COUNT 0xFFC41148 /* DMA2 Bandwidth Monitor Count */ 1578 #define DMA2_CURR_BWM_COUNT 0xFFC4114C /* DMA2 Bandwidth Monitor Count Current */
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/linux-4.4.14/arch/m32r/include/asm/ |
H A D | m32102.h | 254 #define M32R_IRQ_DMA2 (34) /* DMA2 */
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/linux-4.4.14/sound/soc/fsl/ |
H A D | mpc8610_hpcd.c | 42 unsigned int dma_id[2]; /* 0 = DMA1, 1 = DMA2, etc */
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H A D | p1022_rdk.c | 81 unsigned int dma_id[2]; /* 0 = DMA1, 1 = DMA2, etc */
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H A D | p1022_ds.c | 75 unsigned int dma_id[2]; /* 0 = DMA1, 1 = DMA2, etc */
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/linux-4.4.14/drivers/parisc/ |
H A D | superio.c | 59 * 0x5B: RTC, 8259, 8254, DMA1, DMA2, KBC, P61, APM
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/linux-4.4.14/drivers/net/ethernet/freescale/fs_enet/ |
H A D | mac-scc.c | 298 W16(ep, sen_maxd2, 0x000005f0); /* maximum DMA2 length */ restart()
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H A D | mac-fcc.c | 347 W16(ep, fen_maxd2, 1520); /* maximum DMA2 length */ restart()
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/linux-4.4.14/drivers/media/i2c/ |
H A D | saa717x.c | 665 7-4: DMA2, 3-0: DMA1 ch. DMA4, DMA3 DMA2, DMA1
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/linux-4.4.14/drivers/dma/ppc4xx/ |
H A D | adma.c | 301 * operation in DMA2 controller 824 * DMA2 PQ operation 1356 * (1) either using Biskup method on DMA2; ppc440spe_adma_estimate() 1370 ef = 0; /* can't process on DMA2 if !rxor */ ppc440spe_adma_estimate() 2990 /* DMA2 descriptors have only 1 destination, so there are ppc440spe_adma_pq_set_dest() 3204 /* DMA2 may do Biskup */ ppc440spe_adma_pq_set_src() 3253 * ppc440spe_adma_dma2rxor_prep_src - setup RXOR types in DMA2 CDB 3298 "DMA2 RXOR command block.\n"); ppc440spe_adma_dma2rxor_prep_src()
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/linux-4.4.14/drivers/staging/comedi/drivers/ |
H A D | ni_atmio16d.c | 580 options[4] - DMA2 channel
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H A D | s626.h | 135 #define S626_PSR_A2_IN 0x00008000 /* Audio output DMA2 protection
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/linux-4.4.14/drivers/scsi/ |
H A D | esp_scsi.h | 245 * even run that fast with an ESP even with DMA2 scatter gather pipelining.
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/linux-4.4.14/drivers/media/platform/exynos4-is/ |
H A D | fimc-is-param.h | 914 /* Offset to the ISP DMA2 output buffer address array. */
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/linux-4.4.14/include/sound/ |
H A D | gus.h | 307 int dma2; /* DMA2 number */
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/linux-4.4.14/arch/m68k/include/asm/ |
H A D | m68360_pram.h | 349 unsigned short maxd2; /* maximum DMA2 length reg */
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H A D | commproc.h | 391 ushort sen_maxd2; /* maximum DMA2 length */
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/linux-4.4.14/sound/isa/ad1816a/ |
H A D | ad1816a_lib.c | 630 snd_printk(KERN_ERR "ad1816a: can't grab DMA2 %d\n", dma2); snd_ad1816a_create()
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/linux-4.4.14/sound/isa/wavefront/ |
H A D | wavefront.c | 73 MODULE_PARM_DESC(dma2, "DMA2 # for CS4232 PCM interface.");
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/linux-4.4.14/sound/isa/opti9xx/ |
H A D | miro.c | 1475 snd_printk(KERN_ERR "unable to find a free DMA2\n"); snd_miro_isa_probe()
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H A D | opti92x-ad1848.c | 1004 snd_printk(KERN_ERR "unable to find a free DMA2\n"); snd_opti9xx_isa_probe()
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/linux-4.4.14/sound/oss/ |
H A D | waveartist.c | 2044 module_param(dma2, int, 0); /* DMA2 */
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/linux-4.4.14/sound/isa/wss/ |
H A D | wss_lib.c | 1855 snd_printk(KERN_ERR "wss: can't grab DMA2 %d\n", dma2); snd_wss_create()
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/linux-4.4.14/sound/pci/ice1712/ |
H A D | ice1724.c | 470 * Playback DMA2 = playback_con_substream_ds[1] snd_vt1724_interrupt()
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/linux-4.4.14/drivers/tty/serial/ |
H A D | crisv10.c | 229 /* DMA2(ser2), DMA4(ser3), DMA6(ser0) or DMA8(ser1) */ 1880 this interrupt is called from DMA2(ser2), DMA4(ser3), DMA6(ser0) or
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