Searched refs:DMA10 (Results 1 - 9 of 9) sorted by relevance

/linux-4.4.14/arch/blackfin/mach-bf533/include/mach/
H A Dirq.h36 #define IRQ_MEM_DMA1 BFIN_IRQ(22) /* DMA10/11 Interrupt (Memory DMA Stream 1) */
/linux-4.4.14/arch/blackfin/mach-bf537/include/mach/
H A Dirq.h27 #define IRQ_UART1_RX BFIN_IRQ(13) /* DMA10 Interrupt (UART1 RX) */
/linux-4.4.14/arch/blackfin/mach-bf518/include/mach/
H A Dirq.h39 #define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
/linux-4.4.14/arch/blackfin/mach-bf527/include/mach/
H A Dirq.h36 #define IRQ_UART1_RX BFIN_IRQ(24) /* DMA10 Channel (UART1 RX) */
/linux-4.4.14/arch/blackfin/mach-bf609/include/mach/
H A Dirq.h77 #define IRQ_RSI BFIN_IRQ(61) /* RSI (DMA10) Interrupt */
H A DdefBF60x_base.h1728 DMA10
1730 #define DMA10_NEXT_DESC_PTR 0xFFC05000 /* DMA10 Pointer to Next Initial Descriptor */
1731 #define DMA10_START_ADDR 0xFFC05004 /* DMA10 Start Address of Current Buffer */
1732 #define DMA10_CONFIG 0xFFC05008 /* DMA10 Configuration Register */
1733 #define DMA10_X_COUNT 0xFFC0500C /* DMA10 Inner Loop Count Start Value */
1734 #define DMA10_X_MODIFY 0xFFC05010 /* DMA10 Inner Loop Address Increment */
1735 #define DMA10_Y_COUNT 0xFFC05014 /* DMA10 Outer Loop Count Start Value (2D only) */
1736 #define DMA10_Y_MODIFY 0xFFC05018 /* DMA10 Outer Loop Address Increment (2D only) */
1737 #define DMA10_CURR_DESC_PTR 0xFFC05024 /* DMA10 Current Descriptor Pointer */
1738 #define DMA10_PREV_DESC_PTR 0xFFC05028 /* DMA10 Previous Initial Descriptor Pointer */
1739 #define DMA10_CURR_ADDR 0xFFC0502C /* DMA10 Current Address */
1740 #define DMA10_IRQ_STATUS 0xFFC05030 /* DMA10 Status Register */
1741 #define DMA10_CURR_X_COUNT 0xFFC05034 /* DMA10 Current Count(1D) or intra-row XCNT (2D) */
1742 #define DMA10_CURR_Y_COUNT 0xFFC05038 /* DMA10 Current Row Count (2D only) */
1743 #define DMA10_BWL_COUNT 0xFFC05040 /* DMA10 Bandwidth Limit Count */
1744 #define DMA10_CURR_BWL_COUNT 0xFFC05044 /* DMA10 Bandwidth Limit Count Current */
1745 #define DMA10_BWM_COUNT 0xFFC05048 /* DMA10 Bandwidth Monitor Count */
1746 #define DMA10_CURR_BWM_COUNT 0xFFC0504C /* DMA10 Bandwidth Monitor Count Current */
/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/
H A Dirq.h57 #define IRQ_ATAPI_RX BFIN_IRQ(43) /* ATAPI RX (DMA10) Interrupt */
H A DdefBF54x_base.h1559 #define DMA10 0x800 /* DMA Channel 10 */ macro
/linux-4.4.14/drivers/net/ethernet/agere/
H A Det131x.c343 * by 0x101c / 0x1020. This is a DMA10 type

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