| /linux-4.4.14/Documentation/devicetree/bindings/memory-controllers/ |
| D | calxeda-ddr-ctrlr.txt | 1 Calxeda DDR memory controller
7 - reg : Address and size for DDR controller registers.
8 - interrupts : Interrupt for DDR controller.
|
| D | ath79-ddr-controller.txt | 1 Binding for Qualcomm Atheros AR7xxx/AR9xxx DDR controller
3 The DDR controller of the ARxxx and AR9xxx families provides an interface
4 to flush the FIFO between various devices and the DDR. This is mainly used
|
| D | renesas-memory-controllers.txt | 6 by different names ("DDR Bus Controller (DBSC)", "DDR3 Bus State Controller
|
| /linux-4.4.14/Documentation/devicetree/bindings/powerpc/fsl/ |
| D | mem-ctrlr.txt | 1 Freescale DDR memory controller
8 - reg : Address and size of DDR controller registers
9 - interrupts : Error interrupt of DDR controller
|
| D | dcsr.txt | 138 or to a DDR based trace buffer. In some configurations the NPC trace
264 DDR Controller Debug controller
|
| /linux-4.4.14/Documentation/devicetree/bindings/arm/bcm/ |
| D | brcm,brcmstb.txt | 146 independently (control registers, DDR PHYs, etc.). One might consider
161 == DDR PHY control
163 Control registers for this memory controller's DDR PHY.
171 - reg : the DDR PHY register range
173 == DDR SHIMPHY
175 Control registers for this memory controller's DDR SHIMPHY.
179 - reg : the DDR SHIMPHY register range
181 == MEMC DDR control
188 - reg : the MEMC DDR register range
|
| /linux-4.4.14/drivers/gpio/ |
| D | gpio-mb86s7x.c | 35 #define DDR(x) (0x10 + x / 8 * 4) macro
97 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
99 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_input()
122 val = readl(gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
124 writel(val, gchip->base + DDR(gpio)); in mb86s70_gpio_direction_output()
|
| /linux-4.4.14/Documentation/devicetree/bindings/clock/ |
| D | mvebu-core-clock.txt | 12 4 = dramclk (DDR clock)
18 3 = ddrclk (DDR clock)
24 3 = ddrclk (DDR clock)
38 3 = ddrclk (DDR controller clock derived from CPU0 clock)
43 2 = ddrclk (DDR controller clock derived from CPU0 clock)
|
| D | qca,ath79-pll.txt | 3 The PPL controller provides the 3 main clocks of the SoC: CPU, DDR and AHB.
|
| D | pistachio-clock.txt | 47 The peripheral clock controller generates clocks for the DDR, ROM, and other
|
| D | mvebu-gated-clock.txt | 24 28 ddr DDR Cntrl
|
| /linux-4.4.14/drivers/memory/ |
| D | Kconfig | 19 bool "Atmel (Multi-port DDR-)SDRAM Controller"
24 DDR-SDRAM Controller available on Atmel AT91SAM9 and SAMA5 SoCs.
25 Starting with the at91sam9g45, this controller supports SDR, DDR and
26 LP-DDR memories.
42 select DDR
|
| /linux-4.4.14/drivers/mtd/lpddr/ |
| D | Kconfig | 9 flash chips. Synonymous with Mobile-DDR. It is a new standard for
10 DDR memories, intended for battery-operated systems.
|
| /linux-4.4.14/arch/arm/mach-omap2/ |
| D | sleep24xx.S | 69 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, hope SDR/DDR finished
89 movs r0, r0 @ see if DDR or SDR
|
| D | sram242x.S | 152 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
186 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
|
| D | sram243x.S | 152 mcr p15, 0, r3, c7, c10, 4 @ memory barrier, finish ARM SDR/DDR
186 cmp r2, #0x1 @ (SDR or DDR) do we need to adjust DLL
|
| /linux-4.4.14/Documentation/devicetree/bindings/lpddr2/ |
| D | lpddr2-timings.txt | 5 - min-freq : minimum DDR clock frequency for the speed-bin. Type is <u32>
6 - max-freq : maximum DDR clock frequency for the speed-bin. Type is <u32>
|
| D | lpddr2.txt | 20 timing parameters of the DDR device in terms of number of clock cycles.
|
| /linux-4.4.14/Documentation/memory-devices/ |
| D | ti-emif.txt | 34 DDR device details and other board dependent and SoC dependent
36 - DDR device details: 'struct ddr_device_info'
|
| /linux-4.4.14/Documentation/devicetree/bindings/mips/img/ |
| D | xilfpga.txt | 20 - 128Mbyte DDR RAM at 0x0000_0000
74 DDR initialization is already handled by a HW IP block.
|
| /linux-4.4.14/Documentation/arm/Samsung-S3C24XX/ |
| D | S3C2413.txt | 8 interface and mobile DDR memory support. See the S3C2412 support
|
| /linux-4.4.14/drivers/pinctrl/ |
| D | pinctrl-tegra30.c | 2207 …PINGROUP(vi_d1_pd5, DDR, SDMMC2, VI, RSVD4, 0x3128, N, …
2208 …PINGROUP(vi_vsync_pd6, DDR, RSVD2, VI, RSVD4, 0x315c, N, …
2209 …PINGROUP(vi_hsync_pd7, DDR, RSVD2, VI, RSVD4, 0x3160, N, …
2266 …PINGROUP(vi_d2_pl0, DDR, SDMMC2, VI, RSVD4, 0x312c, N, …
2267 …PINGROUP(vi_d3_pl1, DDR, SDMMC2, VI, RSVD4, 0x3130, N, …
2268 …PINGROUP(vi_d4_pl2, DDR, SDMMC2, VI, RSVD4, 0x3134, N, …
2269 …PINGROUP(vi_d5_pl3, DDR, SDMMC2, VI, RSVD4, 0x3138, N, …
2270 …PINGROUP(vi_d6_pl4, DDR, SDMMC2, VI, RSVD4, 0x313c, N, …
2271 …PINGROUP(vi_d7_pl5, DDR, SDMMC2, VI, RSVD4, 0x3140, N, …
2272 …PINGROUP(vi_d8_pl6, DDR, SDMMC2, VI, RSVD4, 0x3144, N, …
[all …]
|
| /linux-4.4.14/arch/mips/include/asm/mach-loongson64/ |
| D | loongson.h | 354 LOONGSON_ADDRWIN_CFG(CPU, DDR, win, src, dst, size)
356 LOONGSON_ADDRWIN_CFG(PCIDMA, DDR, win, src, dst, size)
|
| /linux-4.4.14/Documentation/devicetree/bindings/interrupt-controller/ |
| D | qca,ath79-cpu-intc.txt | 3 On most SoC the IRQ controller need to flush the DDR FIFO before running
|
| /linux-4.4.14/Documentation/devicetree/bindings/media/i2c/ |
| D | tc358743.txt | 23 is half of the bps per lane due to DDR transmission.
|
| /linux-4.4.14/Documentation/devicetree/bindings/powerpc/4xx/ |
| D | cpm.txt | 38 is available to put the DDR in self
|
| /linux-4.4.14/lib/ |
| D | Kconfig | 472 config DDR config
473 bool "JEDEC DDR data"
475 Data from JEDEC specs for DDR SDRAM memories,
478 DDR SDRAM controllers.
|
| /linux-4.4.14/Documentation/devicetree/bindings/memory-controllers/ti/ |
| D | emif.txt | 13 - phy-type : <u32> indicating the DDR phy type. Following are the
|
| /linux-4.4.14/Documentation/devicetree/bindings/mmc/ |
| D | mmc.txt | 43 - mmc-ddr-1_8v: eMMC high-speed DDR mode(1.8V I/O) is supported
44 - mmc-ddr-1_2v: eMMC high-speed DDR mode(1.2V I/O) is supported
|
| D | exynos-dw-mshc.txt | 48 Valid values for SDR and DDR CIU clock timing for Exynos5250:
|
| /linux-4.4.14/arch/arm64/boot/dts/amd/ |
| D | amd-seattle-soc.dtsi | 58 /* DDR range is 40-bit addressing */
|
| /linux-4.4.14/Documentation/devicetree/bindings/media/ |
| D | stih407-c8sectpfe.txt | 5 stream data into the SoC on the TS pins, and into DDR for further processing.
|
| /linux-4.4.14/arch/blackfin/ |
| D | Kconfig | 505 This sets the frequency of the system clock (including SDRAM or DDR) on
533 int "DDR Clock Divider"
538 This sets the frequency of the DDR memory.
540 DDR Clock = (PLL frequency) / (this setting)
543 prompt "DDR SDRAM Chip Type"
556 prompt "DDR/SDRAM Timing"
560 This option allows you to specify Blackfin SDRAM/DDR Timing parameters
|
| /linux-4.4.14/Documentation/devicetree/bindings/arm/ |
| D | fsl.txt | 81 For the Vybrid SoC familiy all variants with DDR controller are supported,
|
| D | atmel-at91.txt | 105 RAMC SDRAM/DDR Controller required properties:
|
| /linux-4.4.14/Documentation/input/ |
| D | xpad.txt | 65 left+right or up+down, making DDR style games unplayable.
206 S: Product=XBOX DDR
|
| D | joystick-parport.txt | 337 * PSX DDR Pad
455 8 | Sony PSX DDR controller
|
| /linux-4.4.14/Documentation/misc-devices/ |
| D | spear-pcie-gadget.txt | 84 Program BAR0 Address as DDR (0x2100000). This is the physical address of
|
| /linux-4.4.14/drivers/edac/ |
| D | Kconfig | 380 tristate "Synopsys DDR Memory Controller"
383 Support for error detection and correction on the Synopsys DDR
|
| /linux-4.4.14/Documentation/hwmon/ |
| D | abituguru-datasheet | 190 Sensor 4 DDR volt
191 Sensor 10 DDR Vtt volt
|
| /linux-4.4.14/arch/arm/mach-tegra/ |
| D | sleep-tegra20.S | 516 bne emcself @ loop until DDR in self-refresh
|
| D | sleep-tegra30.S | 786 bne emcself @ loop until DDR in self-refresh
|
| /linux-4.4.14/drivers/mmc/host/ |
| D | omap_hsmmc.c | 100 #define DDR (1 << 19) macro
687 con |= DDR; /* configure in DDR mode */ in omap_hsmmc_set_bus_width()
689 con &= ~DDR; in omap_hsmmc_set_bus_width()
|
| /linux-4.4.14/arch/arm/boot/dts/ |
| D | omap5.dtsi | 833 phy-type = <2>; /* DDR PHY type: Intelli PHY */
845 phy-type = <2>; /* DDR PHY type: Intelli PHY */
|
| D | stih416-clock.dtsi | 726 * DDR PLL
|
| D | sun6i-a31.dtsi | 747 * data lines in RGMII mode use DDR mode
|
| D | sun7i-a20.dtsi | 1019 * data lines in RGMII mode use DDR mode
|
| D | r8a7791.dtsi | 1566 /* Map all possible DDR as inbound ranges */
|
| D | r8a7790.dtsi | 1576 /* Map all possible DDR as inbound ranges */
|
| /linux-4.4.14/Documentation/ |
| D | edac.txt | 257 Registered-DDR
258 Unbuffered-DDR
|
| /linux-4.4.14/arch/blackfin/mach-bf609/ |
| D | Kconfig | 34 bool "SCB0 Master Interface 0 (DDR)"
|
| /linux-4.4.14/drivers/hid/ |
| D | Kconfig | 778 Note that DDR (Dance Dance Revolution) mode is not supported, nor
|