Home
last modified time | relevance | path

Searched refs:DC_HPD5_INT_CONTROL (Results 1 – 8 of 8) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
Devergreen.c1796 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_hpd_set_polarity()
1801 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_hpd_set_polarity()
4593 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in evergreen_disable_interrupt_state()
4594 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_disable_interrupt_state()
4627 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in evergreen_irq_set()
4810 WREG32(DC_HPD5_INT_CONTROL, hpd5); in evergreen_irq_set()
4922 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4924 WREG32(DC_HPD5_INT_CONTROL, tmp); in evergreen_irq_ack()
4927 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
4953 tmp = RREG32(DC_HPD5_INT_CONTROL); in evergreen_irq_ack()
[all …]
Dr600.c894 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_hpd_set_polarity()
899 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_hpd_set_polarity()
3595 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in r600_disable_interrupt_state()
3596 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_disable_interrupt_state()
3743 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~DC_HPDx_INT_EN; in r600_irq_set()
3839 WREG32(DC_HPD5_INT_CONTROL, hpd5); in r600_irq_set()
3943 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_irq_ack()
3945 WREG32(DC_HPD5_INT_CONTROL, tmp); in r600_irq_ack()
3948 tmp = RREG32(DC_HPD5_INT_CONTROL); in r600_irq_ack()
Dsi.c5987 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in si_disable_interrupt_state()
5988 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_disable_interrupt_state()
6095 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in si_irq_set()
6233 WREG32(DC_HPD5_INT_CONTROL, hpd5); in si_irq_set()
6333 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6335 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_irq_ack()
6338 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6364 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
6366 WREG32(DC_HPD5_INT_CONTROL, tmp); in si_irq_ack()
6369 tmp = RREG32(DC_HPD5_INT_CONTROL); in si_irq_ack()
Dcik.c7362 tmp = RREG32(DC_HPD5_INT_CONTROL) & DC_HPDx_INT_POLARITY; in cik_disable_interrupt_state()
7363 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_disable_interrupt_state()
7489 hpd5 = RREG32(DC_HPD5_INT_CONTROL) & ~(DC_HPDx_INT_EN | DC_HPDx_RX_INT_EN); in cik_irq_set()
7643 WREG32(DC_HPD5_INT_CONTROL, hpd5); in cik_irq_set()
7760 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7762 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7765 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7790 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
7792 WREG32(DC_HPD5_INT_CONTROL, tmp); in cik_irq_ack()
7795 tmp = RREG32(DC_HPD5_INT_CONTROL); in cik_irq_ack()
Dsid.h884 #define DC_HPD5_INT_CONTROL 0x6050 macro
Dcikd.h960 #define DC_HPD5_INT_CONTROL 0x6050 macro
Devergreend.h1350 #define DC_HPD5_INT_CONTROL 0x6050 macro
Dr600d.h861 #define DC_HPD5_INT_CONTROL 0x7dc4 macro