Searched refs:DATA_SEL (Results 1 – 12 of 12) sorted by relevance
249 #define DATA_SEL(x) ((x) << 29) macro
364 #define DATA_SEL(x) ((x) << 29) macro
2473 DATA_SEL(1) | INT_SEL(0)); in gfx_v7_0_ring_emit_fence_gfx()2485 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_gfx()2512 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v7_0_ring_emit_fence_compute()
4631 DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_gfx()4779 amdgpu_ring_write(ring, DATA_SEL(write64bit ? 2 : 1) | INT_SEL(int_sel ? 2 : 0)); in gfx_v8_0_ring_emit_fence_compute()
1248 #define DATA_SEL(x) ((x) << 29) macro
1761 #define DATA_SEL(x) ((x) << 29) macro
1837 #define DATA_SEL(x) ((x) << 29) macro
1673 #define DATA_SEL(x) ((x) << 29) macro
1426 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in cayman_fence_ring_emit()
3978 DATA_SEL(1) | INT_SEL(0)); in cik_fence_gfx_ring_emit()3989 radeon_ring_write(ring, (upper_32_bits(addr) & 0xffff) | DATA_SEL(1) | INT_SEL(2)); in cik_fence_gfx_ring_emit()4015 radeon_ring_write(ring, DATA_SEL(1) | INT_SEL(2)); in cik_fence_compute_ring_emit()
2886 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in r600_fence_ring_emit()
3393 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff) | DATA_SEL(1) | INT_SEL(2)); in si_fence_ring_emit()