Searched refs:CWL (Results 1 - 4 of 4) sorted by relevance
| /linux-4.4.14/drivers/gpu/drm/nouveau/nvkm/subdev/fb/ |
| H A D | sddr3.c | 71 int CWL, CL, WR, DLL = 0, ODT = 0; nvkm_sddr3_calc() local
78 /* XXX: NV50: Get CWL from the timing register */ nvkm_sddr3_calc()
81 CWL = ram->next->bios.timing_10_CWL; nvkm_sddr3_calc()
87 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; nvkm_sddr3_calc()
99 CWL = ramxlat(ramddr3_cwl, CWL); nvkm_sddr3_calc()
102 if (CL < 0 || CWL < 0 || WR < 0) nvkm_sddr3_calc()
117 ram->mr[2] |= (CWL & 0x07) << 3; nvkm_sddr3_calc()
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| H A D | gddr3.c | 73 int CL, WR, CWL, DLL = 0, ODT = 0, RON, hi; nvkm_gddr3_calc() local
77 CWL = ram->next->bios.timing_10_CWL; nvkm_gddr3_calc()
85 CWL = (ram->next->bios.timing[1] & 0x00000f80) >> 7; nvkm_gddr3_calc()
104 if (CL < 0 || CWL < 1 || CWL > 7 || WR < 0) nvkm_gddr3_calc()
108 ram->mr[0] |= (CWL & 0x07) << 9; nvkm_gddr3_calc()
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| H A D | ramnv50.c | 86 switch ((!T(CWL)) * ram->base.type) { nv50_ram_timing_calc()
88 T(CWL) = T(CL) - 1; nv50_ram_timing_calc()
91 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; nv50_ram_timing_calc()
98 timing[6] = (0x2d + T(CL) - T(CWL) + nv50_ram_timing_calc()
100 T(CWL) << 8 | nv50_ram_timing_calc()
101 (0x2f + T(CL) - T(CWL)); nv50_ram_timing_calc()
104 timing[6] = (0x2b + T(CL) - T(CWL)) << 16 | nv50_ram_timing_calc()
105 max_t(s8, T(CWL) - 2, 1) << 8 | nv50_ram_timing_calc()
106 (0x2e + T(CL) - T(CWL)); nv50_ram_timing_calc()
110 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | nv50_ram_timing_calc()
112 (T(WTR) + 1 + T(CWL)) << 8 | nv50_ram_timing_calc()
113 (3 + T(CL) - T(CWL)); nv50_ram_timing_calc()
114 timing[2] = (T(CWL) - 1) << 24 | nv50_ram_timing_calc()
167 T(CWL) = T(CL) - 1; nv50_ram_timing_read()
170 T(CWL) = ((timing[2] & 0xff000000) >> 24) + 1; nv50_ram_timing_read()
177 T(WR) = ((timing[1] >> 24) & 0xff) - 1 - T(CWL); nv50_ram_timing_read()
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| H A D | ramgt215.c | 362 switch ((!T(CWL)) * ram->base.type) { gt215_ram_timing_calc()
364 T(CWL) = T(CL) - 1; gt215_ram_timing_calc()
367 T(CWL) = ((cur2 & 0xff000000) >> 24) + 1; gt215_ram_timing_calc()
375 timing[1] = (T(WR) + 1 + T(CWL)) << 24 | gt215_ram_timing_calc()
377 (T(WTR) + 1 + T(CWL)) << 8 | gt215_ram_timing_calc()
378 (5 + T(CL) - T(CWL)); gt215_ram_timing_calc()
379 timing[2] = (T(CWL) - 1) << 24 | gt215_ram_timing_calc()
393 max_t(u8, (T(CWL) + 6), (T(CL) + 2)) << 8 | gt215_ram_timing_calc()
396 max_t(u8, 1, (6 - T(CL) + T(CWL))) << 8 | gt215_ram_timing_calc()
397 (0x50 + T(CL) - T(CWL)); gt215_ram_timing_calc()
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