Searched refs:CTR (Results 1 - 71 of 71) sorted by relevance

/linux-4.4.14/drivers/staging/comedi/drivers/
H A Damplc_dio200.c44 * 1 CTR-Y1 PPI-Y PPI-Y
45 * 2 CTR-Y2 CTR-Z1* CTR-Z1
46 * 3 CTR-Z1 INTERRUPT* CTR-Z2
47 * 4 CTR-Z2 INTERRUPT
53 * 0 CTR-X1 PPI-X
54 * 1 CTR-X2 PPI-Y
55 * 2 CTR-Y1 PPI-Z
56 * 3 CTR-Y2 INTERRUPT
57 * 4 CTR-Z1
58 * 5 CTR-Z2
71 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
152 * 2 CTR-Y1-OUT1 PPI-Y-C0
153 * 3 CTR-Y2-OUT1 PPI-Y-C3
154 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1
155 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1
160 * 0 CTR-X1-OUT1 PPI-X-C0
161 * 1 CTR-X2-OUT1 PPI-X-C3
162 * 2 CTR-Y1-OUT1 PPI-Y-C0
163 * 3 CTR-Y2-OUT1 PPI-Y-C3
164 * 4 CTR-Z1-OUT1 PPI-Z-C0
165 * 5 CTR-Z2-OUT1 PPI-Z-C3
H A Damplc_dio200_pci.c43 * 2 CTR-Z1 PPI-Y UNUSED
44 * 3 CTR-Z2 UNUSED UNUSED
45 * 4 INTERRUPT CTR-Z1 CTR-Z1
46 * 5 CTR-Z2 CTR-Z2
58 * 4 CTR-Z1
59 * 5 CTR-Z2
73 * Each CTR is a 8254 chip providing 3 16-bit counter channels. Each
187 * 4 CTR-Z1-OUT1 CTR-Z1-OUT1 CTR-Z1-OUT1
188 * 5 CTR-Z2-OUT1 CTR-Z2-OUT1 CTR-Z2-OUT1
197 * 4 PPI-Z-C0 CTR-Z1-OUT1
198 * 5 PPI-Z-C3 CTR-Z2-OUT1
H A Damplc_dio200_common.c47 * 'which' is: 0 for CTR-X1, CTR-Y1, CTR-Z1; 1 for CTR-X2, CTR-Y2 or CTR-Z2.
/linux-4.4.14/include/crypto/
H A Dctr.h2 * CTR: Counter mode
/linux-4.4.14/arch/powerpc/kvm/
H A Dbook3s_32_sr.S37 * SVCPU[CTR] = guest CTR
94 * SVCPU[CTR] = guest CTR
H A Dbook3s_64_slb.S42 * SVCPU[CTR] = guest CTR
109 * SVCPU[CTR] = guest CTR
H A Dbook3s_segment.S69 * SVCPU[CTR] = guest CTR
/linux-4.4.14/arch/x86/crypto/
H A Daesni-intel_avx-x86_64.S357 .macro INITIAL_BLOCKS_AVX num_initial_blocks T1 T2 T3 T4 T5 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T6 T_key ENC_DEC
399 vmovdqu (%rax), \CTR # CTR = Y0
400 vpshufb SHUF_MASK(%rip), \CTR, \CTR
406 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
407 vmovdqa \CTR, reg_i
486 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
487 vmovdqa \CTR, \XMM1
490 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
491 vmovdqa \CTR, \XMM2
494 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
495 vmovdqa \CTR, \XMM3
498 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
499 vmovdqa \CTR, \XMM4
502 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
503 vmovdqa \CTR, \XMM5
506 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
507 vmovdqa \CTR, \XMM6
510 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
511 vmovdqa \CTR, \XMM7
514 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
515 vmovdqa \CTR, \XMM8
633 .macro GHASH_8_ENCRYPT_8_PARALLEL_AVX T1 T2 T3 T4 T5 T6 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T7 loop_idx ENC_DEC
645 vpaddd ONE(%rip), \CTR, \XMM1 # INCR CNT
653 vmovdqa \XMM8, \CTR
664 vpaddd ONEf(%rip), \CTR, \XMM1 # INCR CNT
672 vmovdqa \XMM8, \CTR
1616 .macro INITIAL_BLOCKS_AVX2 num_initial_blocks T1 T2 T3 T4 T5 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T6 T_key ENC_DEC VER
1658 vmovdqu (%rax), \CTR # CTR = Y0
1659 vpshufb SHUF_MASK(%rip), \CTR, \CTR
1665 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1666 vmovdqa \CTR, reg_i
1746 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1747 vmovdqa \CTR, \XMM1
1750 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1751 vmovdqa \CTR, \XMM2
1754 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1755 vmovdqa \CTR, \XMM3
1758 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1759 vmovdqa \CTR, \XMM4
1762 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1763 vmovdqa \CTR, \XMM5
1766 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1767 vmovdqa \CTR, \XMM6
1770 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1771 vmovdqa \CTR, \XMM7
1774 vpaddd ONE(%rip), \CTR, \CTR # INCR Y0
1775 vmovdqa \CTR, \XMM8
1897 .macro GHASH_8_ENCRYPT_8_PARALLEL_AVX2 T1 T2 T3 T4 T5 T6 CTR XMM1 XMM2 XMM3 XMM4 XMM5 XMM6 XMM7 XMM8 T7 loop_idx ENC_DEC
1909 vpaddd ONE(%rip), \CTR, \XMM1 # INCR CNT
1917 vmovdqa \XMM8, \CTR
1928 vpaddd ONEf(%rip), \CTR, \XMM1 # INCR CNT
1936 vmovdqa \XMM8, \CTR
H A Daes_ctrby8_avx-x86_64.S2 * Implement AES CTR mode by8 optimization with AVX instructions. (x86_64)
4 * This is AES128/192/256 CTR mode optimization implementation. It requires
7 * This work was inspired by the AES CTR mode optimization published
544 * routine to do AES128 CTR enc/decrypt "by8"
557 * routine to do AES192 CTR enc/decrypt "by8"
570 * routine to do AES256 CTR enc/decrypt "by8"
H A Daesni-intel_asm.S121 #define CTR %xmm11 define
2551 * CTR: == IV, in little endian
2552 * TCTR_LOW: == lower qword of CTR
2559 movaps IV, CTR
2560 PSHUFB_XMM BSWAP_MASK CTR
2563 MOVQ_R64_XMM CTR TCTR_LOW
2572 * CTR: == IV, in little endian
2573 * TCTR_LOW: == lower qword of CTR
2579 * CTR: == output IV, in little endian
2580 * TCTR_LOW: == lower qword of CTR
2584 paddq INC, CTR
2588 paddq INC, CTR
2591 movaps CTR, IV
2666 * CTR: == temporary value
2669 pshufd $0x13, IV, CTR; \
2671 psrad $31, CTR; \
2672 pand GF128MUL_MASK, CTR; \
2673 pxor CTR, IV;
H A Dblowfish_glue.c8 * CTR part based on code (crypto/ctr.c) by:
H A Ddes3_ede_glue.c8 * CTR part based on code (crypto/ctr.c) by:
H A Dglue_helper.c8 * CTR part based on code (crypto/ctr.c) by:
H A Dserpent_sse2_glue.c12 * CTR part based on code (crypto/ctr.c) by:
H A Dcamellia-aesni-avx-asm_64.S588 /* For CTR-mode IV byteswap */
H A Daesni-intel_glue.c1488 pr_info("AES CTR mode by8 optimization enabled\n"); aesni_init()
H A Dcamellia-aesni-avx2-asm_64.S626 /* For CTR-mode IV byteswap */
/linux-4.4.14/arch/alpha/oprofile/
H A Dop_model_ev6.c74 /* CTR is a counter for which the user has requested an interrupt count
76 for CTR to the value stored in REG->RESET_VALUES. */
H A Dop_model_ev5.c144 /* CTR is a counter for which the user has requested an interrupt count
146 for CTR to the value stored in REG->RESET_VALUES.
H A Dop_model_ev67.c79 /* CTR is a counter for which the user has requested an interrupt count
81 for CTR to the value stored in REG->RESET_VALUES. */
/linux-4.4.14/arch/powerpc/crypto/
H A Daes-spe-regs.h19 #define rIP r8 /* potiner to IV (CBC/CTR/XTS modes) */
H A Daes-spe-core.S63 * have also been set up before (rT0, rKP, CTR). Output is stored in rD0-rD3
211 * have also been set up before (rT0, rKP, CTR). Output is stored in rD0-rD3
H A Daes-spe-modes.S2 * AES modes (ECB/CBC/CTR/XTS) for PPC AES implementation
31 #define CTR_DEC 1 /* CTR decrement one byte */
416 * via CTR. Number of bytes does not need to be a multiple of
H A Daes-spe-glue.c505 MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS, SPE optimized");
/linux-4.4.14/tools/testing/selftests/powerpc/switch_endian/
H A Dswitch_endian_test.S61 * It clobbers r9-r12, XER, CTR and CR0-1,5-7.
/linux-4.4.14/drivers/parport/
H A Dparport_gsc.h66 /* Contents of CTR. */
69 /* Bitmask of writable CTR bits. */
H A Dparport_pc.c1447 printk(KERN_INFO "parport 0x%lx (WARNING): CTR: " parport_SPP_supported()
1484 * on these cards actually accesses the CTR.
1490 * We first check to see if ECR is the same as CTR. If not, the low
/linux-4.4.14/arch/sparc/include/asm/
H A Dparport.h155 /* Enable ECP, set bit 2 of the CTR first */ ecpp_probe()
164 /* CTR bit 5 controls direction of port */ ecpp_probe()
H A Dns87303.h40 #define PTR_LPT_REG_DIR 0x80 /* When ECP/EPP: LPT CTR controls direction */
/linux-4.4.14/arch/mips/loongson64/lemote-2f/
H A Dpm.c37 pr_err("i8042.c: Can't read CTR while enabling i8042 kbd port." i8042_enable_kbd_port()
/linux-4.4.14/drivers/input/serio/
H A Di8042.c382 pr_warn("Can't write CTR while closing %s port\n", port_name); i8042_port_close()
716 * verifies success by readinng CTR. Used when testing for presence of AUX
940 * Save the CTR for restore on unload / reboot. i8042_controller_init()
945 pr_err("Unable to get stable CTR read\n"); i8042_controller_init()
953 pr_err("Can't read CTR while initializing i8042\n"); i8042_controller_init()
1000 * Write CTR back. i8042_controller_init()
1004 pr_err("Can't write CTR while initializing i8042\n"); i8042_controller_init()
1034 pr_warn("Can't write CTR while resetting\n"); i8042_controller_reset()
1055 pr_warn("Can't restore CTR\n"); i8042_controller_reset()
1128 * Restore original CTR value and disable all ports i8042_controller_resume()
1137 pr_warn("Can't write CTR to resume, retrying...\n"); i8042_controller_resume()
1140 pr_err("CTR write retry failed\n"); i8042_controller_resume()
/linux-4.4.14/include/linux/
H A Dparport_pc.h19 /* Contents of CTR. */
22 /* Bitmask of writable CTR bits. */
H A Dccp.h98 * @CCP_AES_MODE_CTR: CTR mode
/linux-4.4.14/drivers/crypto/nx/
H A Dnx-aes-ctr.c2 * AES CTR routines supporting the Power 7+ Nest Accelerators driver
H A Dnx-aes-gcm.c265 /* For scenarios where the input message is zero length, AES CTR mode gcm_empty()
/linux-4.4.14/drivers/crypto/vmx/
H A Daes_ctr.c2 * AES CTR routines supporting VMX instructions on the Power 8
H A Dghashp8-ppc.pl17 # version is ~2.1x slower than hardware-assisted AES-128-CTR, ~12x
H A Daesp8-ppc.pl1229 {{{ # CTR procedure[s] #
1343 {{ # Optimized CTR procedure #
/linux-4.4.14/crypto/
H A Dctr.c2 * CTR: Counter mode
468 MODULE_DESCRIPTION("CTR Counter block mode");
H A Ddrbg.c5 * * CTR DRBG with DF with AES-128, AES-192, AES-256 cores
112 * HMAC DRBGs are favored over Hash DRBGs over CTR DRBGs, and
285 * CTR DRBG callback functions
289 #define CRYPTO_DRBG_CTR_STRING "CTR "
302 /* BCC function for CTR DRBG as defined in 10.4.3 */ drbg_ctr_bcc()
379 /* Derivation Function for CTR DRBG as defined in 10.4.2 */ drbg_ctr_df()
499 * update function of CTR DRBG as defined in 10.2.1.2
577 /* Generate function of CTR DRBG as defined in 10.2.1.5.2 */ drbg_ctr_generate()
1253 /* scratchpad is only generated for CTR and Hash */ drbg_alloc_state()
H A Dseqiv.c5 * with a salt. This algorithm is mainly useful for CTR and similar modes.
H A Dtestmgr.h23976 * (Hash, HMAC, CTR) are tested with all permutations of use cases (w/ and
24416 * (Hash, HMAC, CTR) are tested with all permutations of use cases (w/ and
/linux-4.4.14/drivers/spi/
H A Dspi-sh-msiof.c67 #define CTR 0x28 /* Control Register */ macro
109 /* CTR */
216 data = sh_msiof_read(p, CTR); sh_msiof_modify_ctr_wait()
219 sh_msiof_write(p, CTR, data); sh_msiof_modify_ctr_wait()
222 if ((sh_msiof_read(p, CTR) & mask) == set) sh_msiof_modify_ctr_wait()
354 sh_msiof_write(p, CTR, tmp); sh_msiof_spi_set_pin_regs()
/linux-4.4.14/arch/arm64/crypto/
H A Daes-glue.c33 MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS using ARMv8 Crypto Extensions");
46 MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS using ARMv8 NEON");
/linux-4.4.14/drivers/media/pci/cobalt/
H A Dcobalt-i2c.c44 /* CTR[7:0] - Control register */
/linux-4.4.14/drivers/crypto/ccp/
H A Dccp-crypto-aes.c175 /* Initialize the CTR block */ ccp_aes_rfc3686_crypt()
/linux-4.4.14/tools/testing/selftests/powerpc/pmu/ebb/
H A Debb_handler.S31 * CTR | |
/linux-4.4.14/arch/powerpc/include/asm/
H A Dexception-64s.h102 * we need to use CTR to get to the 2nd level handler. So, save/restore it
109 /* ...else CTR is unused and in register. */
H A Depapr_hcalls.h82 * XER, CTR, and LR are currently listed as clobbers because it's uncertain
/linux-4.4.14/arch/arm/crypto/
H A Daesbs-glue.c435 MODULE_DESCRIPTION("Bit sliced AES in CBC/CTR/XTS modes using NEON");
H A Daes-ce-core.S2 * aes-ce-core.S - AES in CBC/CTR/XTS mode using ARMv8 Crypto Extensions
H A Daes-ce-glue.c19 MODULE_DESCRIPTION("AES-ECB/CBC/CTR/XTS using ARMv8 Crypto Extensions");
H A Dbsaes-armv7.pl46 # Add CBC, CTR and XTS subroutines, adapt for kernel use.
/linux-4.4.14/drivers/staging/comedi/
H A Dcomedi.h268 /* Use CTR as single pulsegenerator */
270 /* Use CTR as pulsetraingenerator */
/linux-4.4.14/drivers/scsi/
H A Dimm.c497 * (BSY is inverted at the CTR register) imm_cpp()
1152 * registers. [ CTR and ECP ] __imm_attach()
H A Dppa.c1012 * registers. [ CTR and ECP ] __ppa_attach()
/linux-4.4.14/drivers/crypto/
H A Dixp4xx_crypto.c124 u8 iv[MAX_IVLEN]; /* IV for CBC mode or CTR IV for CTR mode */
H A Dn2_core.c1220 /* AES: ECB CBC and CTR are supported */
/linux-4.4.14/drivers/nfc/st21nfca/
H A Dcore.c797 *skb_push(skb, 1) = 0x1a; /* CTR, see spec:10.2.2.1 */ st21nfca_hci_im_transceive()
/linux-4.4.14/net/nfc/hci/
H A Dcore.c730 *skb_push(skb, 1) = 0; /* CTR, see spec:10.2.2.1 */ hci_transceive()
/linux-4.4.14/arch/powerpc/kernel/
H A Dfadump.c456 else if (reg_id == REG_ID("CTR")) fadump_set_regval()
H A Dentry_32.S225 * along as well. r12, CCR, CTR, XER etc... are left clobbered as
H A Dprocess.c1017 printk("NIP: "REG" LR: "REG" CTR: "REG"\n", show_regs()
H A Dexceptions-64e.S396 mfctr r7; /* save CTR in stackframe */ \
H A Dexceptions-64s.S62 * We can't branch directly so we do it via the CTR which
/linux-4.4.14/arch/arm/kvm/
H A Dcoproc.c619 FUNCTION_FOR32(0, 0, 0, 1, CTR)
/linux-4.4.14/net/mac80211/
H A Dwpa.c340 /* In CCM, the initial vectors (IV) used for CTR mode encryption and CBC ccmp_special_blocks()
/linux-4.4.14/arch/mn10300/kernel/
H A Dmn10300-serial.c847 _debug("CTR=%04hx ICR=%02hx STR=%04x TMD=%02hx TBR=%04hx ICR=%04hx", mn10300_serial_start_tx()
/linux-4.4.14/drivers/crypto/caam/
H A Dcaamalg.c449 * AES-CTR needs to load IV in CONTEXT1 reg aead_set_sh_desc()
1480 * AES-CTR needs to load IV in CONTEXT1 reg ablkcipher_setkey()
2134 * AES-CTR needs to load IV in CONTEXT1 reg init_authenc_job()
/linux-4.4.14/drivers/platform/x86/
H A Dsony-laptop.c725 SNC_HANDLE(CTR, snc_CTR_get, snc_CTR_set, NULL, 1),
/linux-4.4.14/arch/powerpc/xmon/
H A Dppc-opc.c692 for branch on CTR. We only handle the taken/not-taken hint here. */ insert_bdm()

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