| /linux-4.4.14/drivers/net/ethernet/amd/ |
| H A D | am79c961a.h | 48 #define CSR3 3 macro
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| H A D | sun3lance.c | 205 #define CSR3 3 /* misc */ macro
228 /* CSR3 */
506 REGA(CSR3) = CSR3_BSWP | CSR3_ACON | CSR3_BCON; lance_init_ring()
508 REGA(CSR3) = CSR3_BSWP; lance_init_ring()
537 REGA(CSR3) = CSR3_BSWP; lance_start_xmit()
718 REGA(CSR3) = CSR3_BSWP; lance_interrupt()
756 REGA(CSR3) = CSR3_BSWP; lance_interrupt()
929 REGA( CSR3 ) = CSR3_BSWP; set_multicast_list()
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| H A D | a2065.h | 79 * Bit definitions for CSR3
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| H A D | atarilance.c | 306 #define CSR3 3 /* misc */ macro
329 /* CSR3 */
652 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0); lance_open()
743 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0); lance_tx_timeout()
1108 REGA( CSR3 ) = CSR3_BSWP | (lp->cardtype == PAM_CARD ? CSR3_ACON : 0); set_multicast_list()
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| H A D | am79c961a.c | 300 write_rreg (dev->base_addr, CSR3, CSR3_IDONM|CSR3_BABLM|CSR3_DXSUFLO); am79c961_init_for_open()
369 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL); am79c961_close()
643 write_rreg (dev->base_addr, CSR3, CSR3_MASKALL); am79c961_hw_init()
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| H A D | ariadne.h | 65 #define CSR3 0x0300 /* - Interrupt Masks and Deferral Control */ macro
198 * Bit definitions for CSR3 (Interrupt Masks and Deferral Control)
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| H A D | pcnet32.c | 206 #define CSR3 3 macro
463 val = lp->a->read_csr(ioaddr, CSR3); pcnet32_netif_start()
465 lp->a->write_csr(ioaddr, CSR3, val); pcnet32_netif_start()
1359 val = lp->a->read_csr(ioaddr, CSR3); pcnet32_poll()
1361 lp->a->write_csr(ioaddr, CSR3, val); pcnet32_poll()
2197 val = lp->a->read_csr(ioaddr, CSR3); pcnet32_open()
2199 lp->a->write_csr(ioaddr, CSR3, val); pcnet32_open()
2545 val = lp->a->read_csr(ioaddr, CSR3); pcnet32_interrupt()
2547 lp->a->write_csr(ioaddr, CSR3, val); pcnet32_interrupt()
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| H A D | 7990.h | 160 * Bit definitions for CSR3
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| H A D | ni65.c | 153 #define CSR3 0x03 macro
588 writereg(0,CSR3); /* busmaster/no word-swap */ ni65_init_lance()
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| H A D | ariadne.c | 427 lance->RAP = CSR3; /* Interrupt Masks and Deferral Control */ ariadne_open()
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| H A D | declance.c | 1238 /* busmaster_regval (CSR3) should be zero according to the PMAD-AA dec_lance_probe()
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| /linux-4.4.14/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | dwmac100_dma.c | 61 * DMA CSR3 and CSR4, respectively dwmac100_dma_init()
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| H A D | dwmac1000_dma.c | 101 * DMA CSR3 and CSR4, respectively dwmac1000_dma_init()
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| /linux-4.4.14/drivers/net/wan/lmc/ |
| H A D | lmc_var.h | 71 lmc_csrptr_t csr_rxlist; /* CSR3 */
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| /linux-4.4.14/drivers/net/ethernet/dec/tulip/ |
| H A D | xircom_cb.c | 51 #define CSR3 0x18 macro
593 xw32(CSR3, address); /* Receive descr list address */ setup_descriptors()
631 xw32(CSR3, val); /* Receive descriptor address */ remove_descriptors()
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| H A D | tulip.h | 109 CSR3 = 0x18, enumerator in enum:tulip_offsets
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| H A D | tulip_core.c | 332 iowrite32(tp->rx_ring_dma, ioaddr + CSR3); tulip_up()
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| /linux-4.4.14/drivers/net/wireless/ |
| H A D | adm8211.h | 21 __le32 RDB; /* 0x18 CSR3 */
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| /linux-4.4.14/drivers/net/wireless/rt2x00/ |
| H A D | rt2400pci.h | 85 * CSR3: STA MAC address register 0.
87 #define CSR3 0x000c macro
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| H A D | rt2500pci.h | 96 * CSR3: STA MAC address register 0.
98 #define CSR3 0x000c macro
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| H A D | rt2400pci.c | 309 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3, rt2400pci_config_intf()
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| H A D | rt2500pci.c | 315 rt2x00mmio_register_multiwrite(rt2x00dev, CSR3, rt2500pci_config_intf()
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| /linux-4.4.14/arch/alpha/include/asm/ |
| H A D | core_t2.h | 241 unsigned long elcm_mconf; /* CSR3: Configuration. */
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