| /linux-4.4.14/drivers/net/wan/ |
| H A D | sbni.h | 27 CSR1 = 1, enumerator in enum:sbni_reg
43 /* CSR1 mapping */
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| H A D | sbni.c | 102 struct sbni_csr1 csr1; /* current value of CSR1 */
364 outb( PR_RES, ioaddr + CSR1 ); sbni_probe1()
1056 dev->base_addr + CSR1 ); sbni_watchdog()
1100 outb( *(u_char *)&nl->csr1 | PR_RES, dev->base_addr + CSR1 ); card_start()
1125 outb( *(u8 *)&nl->csr1, dev->base_addr + CSR1 ); change_level()
1143 outb( *(unsigned char *)&nl->csr1, dev->base_addr + CSR1 ); timeout_change_level()
1345 outb( *(u8 *)&nl->csr1 | PR_RES, dev->base_addr + CSR1 ); sbni_ioctl()
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| /linux-4.4.14/drivers/media/pci/dt3155/ |
| H A D | dt3155.h | 44 #define CSR1 0x40 macro
77 /* CSR1 bit masks */
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| H A D | dt3155.c | 178 pd->regs + CSR1); dt3155_start_streaming()
198 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1); dt3155_stop_streaming()
263 tmp = ioread32(ipd->regs + CSR1) & (FLD_CRPT_EVEN | FLD_CRPT_ODD); dt3155_irq_handler_even()
268 ipd->regs + CSR1); dt3155_irq_handler_even()
441 FLD_DN_ODD | FLD_DN_EVEN, pd->regs + CSR1); dt3155_init_board()
446 iowrite32(FIFO_EN | SRST, pd->regs + CSR1); dt3155_init_board()
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| /linux-4.4.14/drivers/net/wireless/ |
| H A D | adm8211.h | 17 __le32 TDR; /* 0x08 CSR1 */
97 /* CSR1 - FRCTL (Frame Control Register) */
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| /linux-4.4.14/drivers/net/ethernet/dec/tulip/ |
| H A D | tulip.h | 107 CSR1 = 0x08, enumerator in enum:tulip_offsets
565 iowrite32(0, ioaddr + CSR1); tulip_tx_timeout_complete()
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| H A D | xircom_cb.c | 49 #define CSR1 0x08 macro
532 This is accomplished by writing to the CSR1 port. The documentation
540 xw32(CSR1, 0); trigger_transmit()
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| H A D | interrupt.c | 680 iowrite32(0, ioaddr + CSR1); tulip_interrupt()
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| H A D | tulip_core.c | 707 iowrite32(0, tp->base_addr + CSR1); tulip_start_xmit()
1183 iowrite32(0, ioaddr + CSR1);
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| /linux-4.4.14/drivers/net/ethernet/stmicro/stmmac/ |
| H A D | dwmac_lib.c | 29 /* CSR1 enables the transmit DMA to check for new descriptor */ dwmac_enable_dma_transmission()
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| /linux-4.4.14/drivers/net/wireless/rt2x00/ |
| H A D | rt2400pci.c | 884 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); rt2400pci_init_registers()
888 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); rt2400pci_init_registers()
890 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); rt2400pci_init_registers()
893 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); rt2400pci_init_registers()
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| H A D | rt2500pci.c | 1022 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); rt2500pci_init_registers()
1026 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); rt2500pci_init_registers()
1028 rt2x00mmio_register_read(rt2x00dev, CSR1, ®); rt2500pci_init_registers()
1031 rt2x00mmio_register_write(rt2x00dev, CSR1, reg); rt2500pci_init_registers()
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| H A D | rt2400pci.h | 69 * CSR1: System control register.
74 #define CSR1 0x0004 macro
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| H A D | rt2500pci.h | 80 * CSR1: System control register.
85 #define CSR1 0x0004 macro
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| /linux-4.4.14/drivers/net/wan/lmc/ |
| H A D | lmc_var.h | 69 lmc_csrptr_t csr_txpoll; /* CSR1 */
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| /linux-4.4.14/drivers/net/ethernet/amd/ |
| H A D | ariadne.h | 63 #define CSR1 0x0100 /* - IADR[15:0] */ macro
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| H A D | atarilance.c | 304 #define CSR1 1 /* init block addr (low) */ macro
654 REGA( CSR1 ) = 0; lance_open()
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| H A D | ni65.c | 151 #define CSR1 0x01 macro
590 writereg(pib & 0xffff,CSR1); ni65_init_lance()
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| H A D | sun3lance.c | 203 #define CSR1 1 /* init block addr (low) */ macro
502 REGA(CSR1) = dvma_vtob(&(MEM->init)); lance_init_ring()
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| /linux-4.4.14/arch/alpha/include/asm/ |
| H A D | core_t2.h | 239 unsigned long elcm_mcmd1; /* CSR1: Command Trap 1. */
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