Searched refs:CS (Results 1 - 200 of 339) sorted by relevance

12

/linux-4.4.14/arch/m68k/include/asm/
H A Dm5307sim.h50 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
51 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
52 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
53 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
54 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
55 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
58 #define MCFSIM_CSBAR (MCF_MBAR + 0x98) /* CS Base Address */
59 #define MCFSIM_CSBAMR (MCF_MBAR + 0x9c) /* CS Base Mask */
60 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9e) /* CS 2 Mask reg */
61 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
62 #define MCFSIM_CSMR3 (MCF_MBAR + 0xaa) /* CS 3 Mask reg */
63 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
64 #define MCFSIM_CSMR4 (MCF_MBAR + 0xb6) /* CS 4 Mask reg */
65 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
66 #define MCFSIM_CSMR5 (MCF_MBAR + 0xc2) /* CS 5 Mask reg */
67 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
68 #define MCFSIM_CSMR6 (MCF_MBAR + 0xce) /* CS 6 Mask reg */
69 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
70 #define MCFSIM_CSMR7 (MCF_MBAR + 0xda) /* CS 7 Mask reg */
71 #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
73 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
74 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
75 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
76 #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
77 #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
78 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
79 #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
80 #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
81 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
82 #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
83 #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
84 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
85 #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
86 #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
87 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
88 #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
89 #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
90 #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
H A Dm5206sim.h61 #define MCFSIM_CSAR0 (MCF_MBAR + 0x64) /* CS 0 Address reg */
62 #define MCFSIM_CSMR0 (MCF_MBAR + 0x68) /* CS 0 Mask reg */
63 #define MCFSIM_CSCR0 (MCF_MBAR + 0x6e) /* CS 0 Control reg */
64 #define MCFSIM_CSAR1 (MCF_MBAR + 0x70) /* CS 1 Address reg */
65 #define MCFSIM_CSMR1 (MCF_MBAR + 0x74) /* CS 1 Mask reg */
66 #define MCFSIM_CSCR1 (MCF_MBAR + 0x7a) /* CS 1 Control reg */
67 #define MCFSIM_CSAR2 (MCF_MBAR + 0x7c) /* CS 2 Address reg */
68 #define MCFSIM_CSMR2 (MCF_MBAR + 0x80) /* CS 2 Mask reg */
69 #define MCFSIM_CSCR2 (MCF_MBAR + 0x86) /* CS 2 Control reg */
70 #define MCFSIM_CSAR3 (MCF_MBAR + 0x88) /* CS 3 Address reg */
71 #define MCFSIM_CSMR3 (MCF_MBAR + 0x8c) /* CS 3 Mask reg */
72 #define MCFSIM_CSCR3 (MCF_MBAR + 0x92) /* CS 3 Control reg */
73 #define MCFSIM_CSAR4 (MCF_MBAR + 0x94) /* CS 4 Address reg */
74 #define MCFSIM_CSMR4 (MCF_MBAR + 0x98) /* CS 4 Mask reg */
75 #define MCFSIM_CSCR4 (MCF_MBAR + 0x9e) /* CS 4 Control reg */
76 #define MCFSIM_CSAR5 (MCF_MBAR + 0xa0) /* CS 5 Address reg */
77 #define MCFSIM_CSMR5 (MCF_MBAR + 0xa4) /* CS 5 Mask reg */
78 #define MCFSIM_CSCR5 (MCF_MBAR + 0xaa) /* CS 5 Control reg */
79 #define MCFSIM_CSAR6 (MCF_MBAR + 0xac) /* CS 6 Address reg */
80 #define MCFSIM_CSMR6 (MCF_MBAR + 0xb0) /* CS 6 Mask reg */
81 #define MCFSIM_CSCR6 (MCF_MBAR + 0xb6) /* CS 6 Control reg */
82 #define MCFSIM_CSAR7 (MCF_MBAR + 0xb8) /* CS 7 Address reg */
83 #define MCFSIM_CSMR7 (MCF_MBAR + 0xbc) /* CS 7 Mask reg */
84 #define MCFSIM_CSCR7 (MCF_MBAR + 0xc2) /* CS 7 Control reg */
H A Dm5407sim.h50 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
51 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
52 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
53 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
54 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
55 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
57 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
58 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
59 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
60 #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
61 #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
62 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
63 #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
64 #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
65 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
66 #define MCFSIM_CSAR5 (MCF_MBAR + 0xbc) /* CS 5 Address reg */
67 #define MCFSIM_CSMR5 (MCF_MBAR + 0xc0) /* CS 5 Mask reg */
68 #define MCFSIM_CSCR5 (MCF_MBAR + 0xc6) /* CS 5 Control reg */
69 #define MCFSIM_CSAR6 (MCF_MBAR + 0xc8) /* CS 6 Address reg */
70 #define MCFSIM_CSMR6 (MCF_MBAR + 0xcc) /* CS 6 Mask reg */
71 #define MCFSIM_CSCR6 (MCF_MBAR + 0xd2) /* CS 6 Control reg */
72 #define MCFSIM_CSAR7 (MCF_MBAR + 0xd4) /* CS 7 Address reg */
73 #define MCFSIM_CSMR7 (MCF_MBAR + 0xd8) /* CS 7 Mask reg */
74 #define MCFSIM_CSCR7 (MCF_MBAR + 0xde) /* CS 7 Control reg */
H A Dm525xsim.h54 #define MCFSIM_CSAR0 (MCF_MBAR + 0x80) /* CS 0 Address reg */
55 #define MCFSIM_CSMR0 (MCF_MBAR + 0x84) /* CS 0 Mask reg */
56 #define MCFSIM_CSCR0 (MCF_MBAR + 0x8a) /* CS 0 Control reg */
57 #define MCFSIM_CSAR1 (MCF_MBAR + 0x8c) /* CS 1 Address reg */
58 #define MCFSIM_CSMR1 (MCF_MBAR + 0x90) /* CS 1 Mask reg */
59 #define MCFSIM_CSCR1 (MCF_MBAR + 0x96) /* CS 1 Control reg */
60 #define MCFSIM_CSAR2 (MCF_MBAR + 0x98) /* CS 2 Address reg */
61 #define MCFSIM_CSMR2 (MCF_MBAR + 0x9c) /* CS 2 Mask reg */
62 #define MCFSIM_CSCR2 (MCF_MBAR + 0xa2) /* CS 2 Control reg */
63 #define MCFSIM_CSAR3 (MCF_MBAR + 0xa4) /* CS 3 Address reg */
64 #define MCFSIM_CSMR3 (MCF_MBAR + 0xa8) /* CS 3 Mask reg */
65 #define MCFSIM_CSCR3 (MCF_MBAR + 0xae) /* CS 3 Control reg */
66 #define MCFSIM_CSAR4 (MCF_MBAR + 0xb0) /* CS 4 Address reg */
67 #define MCFSIM_CSMR4 (MCF_MBAR + 0xb4) /* CS 4 Mask reg */
68 #define MCFSIM_CSCR4 (MCF_MBAR + 0xba) /* CS 4 Control reg */
/linux-4.4.14/arch/x86/um/os-Linux/
H A Dmcontext.c17 COPY(EIP); COPY_SEG_CPL3(CS); COPY(EFL); COPY_SEG_CPL3(SS); get_regs_from_mc()
27 COPY2(CS, CSGSFS); get_regs_from_mc()
28 regs->gp[CS / sizeof(unsigned long)] &= 0xffff; get_regs_from_mc()
29 regs->gp[CS / sizeof(unsigned long)] |= 3; get_regs_from_mc()
/linux-4.4.14/arch/powerpc/include/asm/
H A Dmpc5121.h52 u32 cs_cfg[8]; /* CS config */
53 u32 cs_ctrl; /* CS Control Register */
54 u32 cs_status; /* CS Status Register */
55 u32 burst_ctrl; /* CS Burst Control Register */
56 u32 deadcycle_ctrl; /* CS Deadcycle Control Register */
57 u32 holdcycle_ctrl; /* CS Holdcycle Control Register */
H A Dreg_a2.h54 #define MMUCR1_CSINV_ALL 0x00000000 /* Inval ERAT on all CS evts */
56 #define MMUCR1_CSINV_NEVER 0x0c000000 /* Don't inval ERAT on CS */
H A D8xx_immap.h120 #define OR_ACS_DIV1 0x00000000 /* CS is output at the same time */
121 #define OR_ACS_DIV4 0x00000400 /* CS is output 1/4 a clock later */
122 #define OR_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later */
/linux-4.4.14/tools/perf/arch/x86/util/
H A Dperf_regs.c15 SMPL_REG(CS, PERF_REG_X86_CS),
/linux-4.4.14/arch/x86/realmode/rm/
H A Dtrampoline_32.S9 * Entry: CS:IP point to the start of our code, we are
17 * with 16-bit addressing and 16-bit data. CS has some value
18 * and IP is zero. Thus, we load CS to the physical segment
H A Dtrampoline_64.S8 * Entry: CS:IP point to the start of our code, we are
14 * with 16-bit addressing and 16-bit data. CS has some value
114 * with EFER.LME = 1, CS.L = 0, CS.D = 1 (and in turn
116 * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
H A Dreboot.S71 * followed immediately by a far jump instruction, which set CS to a
/linux-4.4.14/tools/perf/arch/x86/tests/
H A Dregs_load.S13 #define CS 10 * 8 define
46 movq $0, CS(%rdi)
83 movl $0, CS(%edi)
/linux-4.4.14/drivers/pcmcia/
H A Dsa1100_shannon.c69 printk(KERN_WARNING "%s(): CS asked for 0V, still applying 3.3V..\n", __func__); shannon_pcmcia_configure_socket()
72 printk(KERN_WARNING "%s(): CS asked for 5V, applying 3.3V..\n", __func__); shannon_pcmcia_configure_socket()
H A Dsa1100_assabet.c52 printk(KERN_WARNING "%s(): CS asked for 5V, applying 3.3V...\n", assabet_pcmcia_configure_socket()
/linux-4.4.14/arch/x86/include/uapi/asm/
H A Dptrace-abi.h19 #define CS 13 macro
55 #define CS 136 macro
H A Dldt.h16 * Note on 64bit base and limit is ignored and you cannot set DS/ES/CS
/linux-4.4.14/include/sound/
H A Dcs8427.h73 #define CS8427_MMTCS (1<<1) /* 0 = use A + B CS data, 1 = use MMTLR CS data */
74 #define CS8427_MMTLR (1<<0) /* 0 = use A CS data, 1 = use B CS data */
167 #define CS8427_BSEL (1<<5) /* 0 = CS data, 1 = U data */
168 #define CS8427_CBMR (1<<4) /* 0 = overwrite first 5 bytes for CS D to E buffer, 1 = prevent */
169 #define CS8427_DETCI (1<<3) /* D to E CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
170 #define CS8427_EFTCI (1<<2) /* E to F CS data buffer transfer inhibit bit, 0 = allow, 1 = inhibit */
171 #define CS8427_CAM (1<<1) /* CS data buffer control port access mode bit, 0 = one byte, 1 = two byte */
/linux-4.4.14/include/video/
H A Dcvisionppc.h5 * Copyright (c) 1998-1999 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
H A Dpermedia2.h3 * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
/linux-4.4.14/arch/x86/um/
H A Duser-offsets.c47 DEFINE(HOST_CS, CS); foo()
72 DEFINE_LONGS(HOST_CS, CS); foo()
H A Dptrace_32.c67 [CS] = HOST_CS,
102 case CS: putreg()
153 case CS: getreg()
H A Dptrace_64.c41 [CS >> 3] = HOST_CS,
89 case CS: putreg()
168 case CS: getreg()
H A Dsignal.c195 GETREG(CS, cs); copy_sc_from_user()
286 PUTREG(CS, cs); copy_sc_to_user()
/linux-4.4.14/include/linux/platform_data/
H A Dspi-s3c64xx.h21 * @line: Custom 'identity' of the CS line.
35 * @num_cs: Number of CS this controller emulates.
H A Dvideo-pxafb.h102 unsigned a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
103 unsigned a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
/linux-4.4.14/arch/m68k/coldfire/
H A Dm527x.c64 /* setup QSPS pins for QSPI with gpio CS control */ m527x_qspi_init()
71 /* setup QSPS pins for QSPI with gpio CS control */ m527x_qspi_init()
H A Dm523x.c60 /* setup QSPS pins for QSPI with gpio CS control */ m523x_qspi_init()
H A Dm528x.c60 /* setup Port QS for QSPI with gpio CS control */ m528x_qspi_init()
H A Dm520x.c125 /* setup Port QS for QSPI with gpio CS control */ m520x_qspi_init()
/linux-4.4.14/include/linux/
H A Domap-gpmc.h84 u32 t_ceasu; /* address setup to CS valid */
100 u32 t_ce; /* access time from CS asertion */
102 u32 t_cez_r; /* read CS deassertion to high Z */
103 u32 t_cez_w; /* write CS deassertion to high Z */
112 u32 t_ces; /* CS setup time to clk */
119 u32 t_ce_avd; /* CS on to ADV on delay */
/linux-4.4.14/arch/mn10300/kernel/
H A Dkprobes.c92 #define CS (1 << 4) macro
110 /* 0 1 0 0 */ (NE | NC | CS | VC | GE | GT | LS),
111 /* 0 1 0 1 */ (EQ | NC | CS | VC | GE | LE | LS),
112 /* 0 1 1 0 */ (NE | NS | CS | VC | LT | LE | LS),
113 /* 0 1 1 1 */ (EQ | NS | CS | VC | LT | LE | LS),
118 /* 1 1 0 0 */ (NE | NC | CS | VS | LT | LE | LS),
119 /* 1 1 0 1 */ (EQ | NC | CS | VS | LT | LE | LS),
120 /* 1 1 1 0 */ (NE | NS | CS | VS | GE | GT | LS),
121 /* 1 1 1 1 */ (EQ | NS | CS | VS | GE | LE | LS),
/linux-4.4.14/arch/x86/include/asm/xen/
H A Dinterface_64.h58 * The saved CS is mapped as follows:
69 * Discard R11, RCX, CS, SS.
71 * Restore RAX, R11, RCX, CS:RIP, RFLAGS, SS:RSP.
H A Dinterface.h235 unsigned long event_callback_cs; /* CS:EIP of event callback */
237 unsigned long failsafe_callback_cs; /* CS:EIP of failsafe callback */
/linux-4.4.14/arch/arm/mach-sa1100/
H A Dh3xxx.c275 { /* static memory bank 2 CS#2 */
280 }, { /* static memory bank 4 CS#4 */
285 }, { /* EGPIO 0 CS#5 */
H A Dgeneric.c83 /* disable internal oscillator, float CS lines */ sa1100_power_off()
H A Dsimpad.c236 /* disable internal oscillator, float CS lines */ simpad_power_off()
/linux-4.4.14/drivers/isdn/hardware/eicon/
H A Dmi_pc.h166 /* I/O CS device coding */
176 #define LOW_BOOTCS_DREG 0x0440 /* Boot CS low decode register */
177 #define HI_BOOTCS_DREG 0x0444 /* Boot CS High decode register */
183 /* I/O CS group coding for (CPU) */
192 #define CS20_BANKSIZE 0x0c10 /* CS 2..0 group PCI bank size */
193 #define CS3B_BANKSIZE 0x0c14 /* CS 3 & Boot group PCI bank size */
/linux-4.4.14/drivers/usb/host/
H A Dxhci-mvebu.c32 /* Program each DRAM CS in a seperate window */ xhci_mvebu_mbus_config()
/linux-4.4.14/drivers/gpu/drm/radeon/
H A Dr100_track.h10 * CS functions
H A Dradeon_cs.c250 /* XXX: note that this is called from the legacy UMS CS ioctl as well */ radeon_cs_parser_init()
723 DRM_ERROR("Can not parse packet at %d after CS end %d !\n", radeon_cs_packet_parse()
753 DRM_ERROR("Packet (%d:%d:%d) end after CS buffer (%d) !\n", radeon_cs_packet_parse()
H A Dradeon_drv.c59 * 2.11.0 - backend map, initial compute support for the CS checker
75 * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
90 * CS to GPU on >= r600
/linux-4.4.14/include/linux/usb/
H A Disp1362.h41 * WE MUST NOT be activated during these intervals (even without CS!)
/linux-4.4.14/arch/arm/kernel/
H A Dopcodes.c25 0xCCCC, /* CS == C set */
/linux-4.4.14/sound/pci/ice1712/
H A Drevo.h49 #define VT1724_REVO_CS2 0x40 /* surround AKM4355 CS (revo71) */
H A Ddelta.h138 #define ICE1712_DELTA_1010LT_CS 0x70 /* mask for CS address */
H A Dphase.c27 * Digital receiver: CS8414-CS (supported in this release)
32 * - CS directly from GPIO 10
42 * Digital receiver: CS8414-CS (supported in this release)
/linux-4.4.14/tools/perf/arch/x86/include/
H A Dperf_regs.h50 return "CS"; perf_reg_name()
/linux-4.4.14/tools/testing/selftests/x86/
H A Dsigreturn.c17 * For now, this focuses on the effects of unusual CS and SS values,
312 * SIGUSR1 handler. Sets CS and SS as requested and points IP to the
413 printf("[WARN]\tCould not find %d-bit CS\n", bitness); find_cs()
421 printf("[SKIP]\tCode segment unavailable for %d-bit CS, %d-bit SS\n", test_valid_sigreturn()
431 printf("[SKIP]\tData segment unavailable for %d-bit CS, 16-bit SS\n", test_valid_sigreturn()
443 printf("[RUN]\tValid sigreturn: %d-bit CS (%hx), %d-bit SS (%hx%s)\n", test_valid_sigreturn()
539 printf("[RUN]\t%d-bit CS (%hx), bogus SS (%hx)\n", test_bad_iret()
603 /* Easy cases: return to a 32-bit SS in each possible CS bitness. */ main()
610 * CS bitness. NB: with a long mode CS, the SS bitness is irrelevant. main()
H A Dentry_from_vm86.c73 printf("[INFO]\t%s: FLAGS = 0x%lx, CS = 0x%hx\n", signame, sighandler()
/linux-4.4.14/arch/blackfin/mach-bf537/boards/
H A Dstamp.c1021 .chip_select = 4, /* CS, change it for your board */
1032 .chip_select = 4, /* CS, change it for your board */
1043 .chip_select = 4, /* CS, change it for your board */
1054 .chip_select = 4, /* CS, change it for your board */
1067 .chip_select = 4, /* CS, change it for your board */
1079 .chip_select = 4, /* CS, change it for your board */
1091 .chip_select = 4, /* CS, change it for your board */
1206 .chip_select = 1, /* CS, change it for your board */
1216 .chip_select = 1, /* CS, change it for your board */
1226 .chip_select = 1, /* CS, change it for your board */
1236 .chip_select = 1, /* CS, change it for your board */
1246 .chip_select = 1, /* CS, change it for your board */
1256 .chip_select = MAX_CTRL_CS + 1, /* CS for read, change it for your board */
1264 .chip_select = 2, /* CS for write, change it for your board */
1274 .chip_select = 1, /* CS for read, change it for your board */
1284 .chip_select = 5, /* CS, change it for your board */
1295 .chip_select = 5, /* CS, change it for your board */
1306 .chip_select = 5, /* CS, change it for your board */
1317 .chip_select = 5, /* CS, change it for your board */
1328 .chip_select = 5, /* CS, change it for your board */
1339 .chip_select = 5, /* CS, change it for your board */
1350 .chip_select = 5, /* CS, change it for your board */
1361 .chip_select = 1, /* CS, change it for your board */
1371 .chip_select = 5, /* CS, change it for your board */
1382 .chip_select = 5, /* CS, change it for your board */
1393 .chip_select = 1, /* CS, change it for your board */
/linux-4.4.14/drivers/spi/
H A Dspi-bcm2835.c49 /* Bitfields in CS */
177 * note that there have been rare events where the native-CS bcm2835_spi_transfer_one_irq()
563 /* for gpio_cs set dummy CS so that no HW-CS get changed bcm2835_spi_transfer_one()
634 * we can also assume that we are CS < 3 as per bcm2835_spi_setup bcm2835_spi_set_cs()
651 /* set the correct CS-bits */ bcm2835_spi_set_cs()
655 /* clean the CS-bits */ bcm2835_spi_set_cs()
672 /* disable CSPOL which puts HW-CS into deselected state */ bcm2835_spi_set_cs()
699 /* error in the case of native CS requested with CS > 1 bcm2835_spi_setup()
714 /* and calculate the real CS */ bcm2835_spi_setup()
718 dev_info(&spi->dev, "setting up native-CS%i as GPIO %i\n", bcm2835_spi_setup()
726 "could not set CS%i gpio %i as output: %i", bcm2835_spi_setup()
H A Dspi-clps711x.c118 dev_err(&pdev->dev, "At least one CS must be defined\n"); spi_clps711x_probe()
152 dev_err(&pdev->dev, "Can't get CS GPIO %i\n", i); spi_clps711x_probe()
H A Dspi-rb4xx.c89 * Setting CS is done along with bitbanging the actual values, rb4xx_set_cs()
91 * CPLD needs CS deselected after every command. rb4xx_set_cs()
H A Dspi-txx9.c110 ndelay(cs_delay); /* CS Hold Time */ txx9spi_cs_func()
113 ndelay(cs_delay); /* CS Setup Time / CS Recovery Time */ txx9spi_cs_func()
159 /* CS setup/hold/recovery time in nsec */ txx9spi_work_one()
H A Dspi-sc18is602.c84 * resembles a full SPI message (from CS active to CS inactive). sc18is602_txrx()
99 * account for CS). sc18is602_txrx()
H A Dspi-dln2.c127 * Select/unselect multiple CS lines. The selected lines will be automatically
154 * Select one CS line. The other lines will be un-selected.
162 * Enable/disable CS lines for usage. The module has to be disabled first.
718 dev_err(&pdev->dev, "Failed to get number of CS pins\n"); dln2_spi_probe()
739 dev_err(&pdev->dev, "Failed to enable CS pins\n"); dln2_spi_probe()
H A Dspi-bcm63xx.c344 * This SPI controller does not support keeping CS active after a bcm63xx_spi_transfer_one()
379 /* CS will be deasserted directly after transfer */ bcm63xx_spi_transfer_one()
381 dev_err(&spi->dev, "unable to keep CS asserted after transfer\n"); bcm63xx_spi_transfer_one()
H A Dspi-mxs.c64 #define TXRX_DEASSERT_CS (1<<1) /* De-assert CS at end of txrx */
214 * De-assert CS on last segment if flag is set (i.e., no more mxs_spi_txrx_dma()
378 /* Program CS register bits here, it will be used for all transfers. */ mxs_spi_transfer_one()
H A Dspi-fsl-espi.c57 /* eSPI Controller CS mode register definitions */
235 /* Set SPCOM[CS] and SPCOM[TRANLEN] field */ fsl_espi_bufs()
701 /* Init eSPI CS mode register */ fsl_espi_probe()
863 /* Init eSPI CS mode register */ of_fsl_espi_resume()
H A Dspi-bcm63xx-hsspi.c267 /* This controller does not support keeping CS active during idle. bcm63xx_hsspi_transfer_one()
394 /* read out default CS polarities */ bcm63xx_hsspi_probe()
H A Dspi-bitbang.c313 /* SPI core provides CS high / low, but bitbang driver spi_bitbang_set_cs()
314 * expects CS active spi_bitbang_set_cs()
H A Dspi-gpio.c240 * In DT environments, the CS GPIOs have already been spi_gpio_setup()
462 * In DT environments, take the CS GPIO from the "cs-gpios" spi_gpio_probe()
H A Dspi-mpc52xx.c94 * CS control function
286 * aren't then deactivate CS, notify sender, and drop back to idle mpc52xx_spi_fsmstate_wait()
H A Dspi-omap-uwire.c186 /* Deselect this CS, or the previous CS */ uwire_chipselect()
H A Dspi-ppc4xx.c428 /* Real CS - set the initial state. */ spi_ppc4xx_of_probe()
439 ; /* No CS, but that's OK. */ spi_ppc4xx_of_probe()
H A Dspi-omap2-mcspi.c100 /* We have 2 DMA channels per CS, one for RX and one for TX */
1097 * chipselect with the FORCE bit ... CS != channel enable. omap2_mcspi_work_one()
1514 * When SPI wake up from off-mode, CS is in activate state. If it was in
1529 * We need to toggle CS state for OMAP take this omap2_mcspi_resume()
H A Dspi-sh-hspi.c148 hspi_write(hspi, SPSCR, 0x21); /* master mode / CS control */ hspi_hw_setup()
H A Dspi-sh-msiof.c526 * Use spi->controller_data for CS (same strategy as spi_gpio), sh_msiof_spi_setup()
527 * if any. otherwise let HW control CS sh_msiof_spi_setup()
532 /* Configure pins before deasserting CS */ sh_msiof_spi_setup()
554 /* Configure pins before asserting CS */ sh_msiof_prepare_message()
H A Dspi-adi-v3.c182 /* enable or disable the pin muxed by GPIO and SPI CS to work as SPI CS */ adi_spi_cs_enable()
H A Dspi-sh.c272 /* deassert CS when SPI is receiving. */ spi_sh_receive()
H A Dspi-davinci.c348 * - 3 pin SPI is a 4 pin variant without CS (SPI_NO_CS) davinci_spi_setup_transfer()
902 * indicated by chip_sel being NULL. GPIO based CS is not spi_davinci_get_pdata()
1079 /* Set up SPIPC0. CS and ENA init is done in davinci_spi_setup */ davinci_spi_probe()
/linux-4.4.14/drivers/mtd/nand/
H A Dcmx270_nand.c146 ret = gpio_request(GPIO_NAND_CS, "NAND CS"); cmx270_init()
148 pr_warning("CM-X270: failed to request NAND CS gpio\n"); cmx270_init()
H A Dsunxi_nand.c202 * @cs: the NAND CS id used to communicate with a NAND Chip
230 * @selected: current active CS
231 * @nsels: number of CS lines required by the NAND chip
232 * @sels: array of CS lines descriptions
259 * @assigned_cs: bitmask describing already assigned CS lines
967 /* TODO: A83 has some more bits for CDQSS, CS, CLHZ, CCS, WC */ sunxi_nand_chip_set_timings()
1274 "invalid reg value: %u (max CS = 7)\n", sunxi_nand_chip_init()
1280 dev_err(dev, "CS %d already assigned\n", tmp); sunxi_nand_chip_init()
H A Dxway_nand.c141 /* load our CS from the DT. Either we find a valid 1 or default to 0 */ xway_nand_probe()
H A Dau1550nd.c392 /* figure out the decoded range of this CS */ find_nand_cs()
444 /* figure out which CS# r->start belongs to */ au1550nd_probe()
H A Dndfc.c216 dev_err(&ofdev->dev, "invalid CS number (%d)\n", cs); ndfc_probe()
H A Dvf610_nfc.c521 * This function supports Vybrid only (MPC5125 would have full RB and four CS)
528 /* Vybrid only (MPC5125 would have full RB and four CS) */ vf610_nfc_select_chip()
H A Dcs553x_nand.c192 printk(KERN_NOTICE "Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio?"MM":"P", adr); cs553x_init_one()
/linux-4.4.14/arch/sparc/include/asm/
H A Dross.h20 * |implvers| RSV |CWR|SE|WBE| MID |BM| C|CS|MR|CM|RSV|CE|RSV|NF|ME|
33 * CS: Cache Size -- 0 = 128k, 1 = 256k
/linux-4.4.14/arch/arm/mach-omap2/
H A Dboard-flash.c77 pr_err("NOR: Can't request GPMC CS\n"); board_nor_init()
170 /* ES2.0 SDP's onwards 4 dip switches are provided for CS */ get_gpmc0_type()
H A Dgpmc-nand.c91 pr_err("omap2-gpmc: Cannot request GPMC CS %d, error %d\n", gpmc_nand_init()
H A Dgpmc-onenand.c394 dev_err(dev, "Cannot request GPMC CS %d, error %d\n", gpmc_onenand_init()
/linux-4.4.14/drivers/staging/iio/resolver/
H A Dad2s90.c86 /* need 600ns between CS and the first falling edge of SCLK */ ad2s90_probe()
/linux-4.4.14/arch/x86/boot/compressed/
H A Defi_stub_32.S28 * 0. The function can only be called in Linux kernel. So CS has been
H A Dhead_64.S175 * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1
177 * the new gdt/idt that has __KERNEL_CS with CS.L = 1.
/linux-4.4.14/arch/x86/include/asm/
H A Dlguest.h82 /* Full 4G segment descriptors, suitable for CS and DS. */
H A Dptrace.h100 * register set was from protected mode with RPL-3 CS value. This
H A Dsegment.h69 * 14 - default user CS
H A Dthread_info.h270 * return path, which is able to restore modified SS, CS and certain
/linux-4.4.14/arch/x86/purgatory/
H A Dentry64.S33 pushq $0x10 /* CS */
/linux-4.4.14/arch/arm/mach-spear/
H A Dspear3xx.c38 * soon as FIFO becomes empty, CS is disabled and transfer ends). So
/linux-4.4.14/sound/usb/
H A Dmixer.h55 unsigned int control; /* CS or ICN (high byte) */
/linux-4.4.14/arch/x86/entry/
H A Dentry_64.S314 cmpq $__USER_CS, CS(%rsp) /* CS must match SYSRET */
452 testb $3, CS(%rsp) /* from kernel_thread? */
504 testb $3, CS(%rsp)
563 testb $3, CS(%rsp)
632 movq (3*8)(%rsp), %rax /* CS */
745 testb $3, CS(%rsp) /* If coming from userspace, switch stacks */
1052 testb $3, CS+8(%rsp)
1196 testb $3, CS-RIP+8(%rsp)
1261 * | original CS |
1271 * | iret CS } iteration if needed. |
1277 * | outermost CS } Copied to "iret" frame on each |
1401 pushq $__KERNEL_CS /* CS */
H A Dentry_64_compat.S148 * or target CS descriptor's L bit (SYSCALL does not read segment descriptors).
227 * CS = __USER32_CS
H A Dcalling.h84 #define CS 17*8 macro
/linux-4.4.14/arch/arm/mach-pxa/
H A Dtrizeps4.c66 GPIO15_nCS_1, /* DiskOnChip CS */
70 GPIO78_nCS_2, /* DM9000 CS */
73 GPIO79_nCS_3, /* Logic CS */
H A Dicontrol.c150 /* CAN CS lines */
H A Dam300epd.c98 "CS", "IRQ", "LED" };
H A Dcolibri-pxa270.c138 GPIO78_nCS_2, /* Ethernet CS */
H A Didp.c68 GPIO33_nCS_5, /* Ethernet CS */
H A Dspitz_pm.c125 /* Stop 3.6MHz and drive HIGH to PCMCIA and CS */ spitz_presuspend()
H A Dz2.c144 GPIO24_GPIO, /* WiFi CS */
146 GPIO88_GPIO, /* LCD CS */
H A Dem-x270.c379 err = gpio_request(GPIO11_NAND_CS, "NAND CS"); em_x270_init_nand()
381 pr_warn("EM-X270: failed to request NAND CS gpio\n"); em_x270_init_nand()
H A Draumfeld.c214 GPIO1_nCS2, /* CS */
270 GPIO1_nCS2, /* CS */
/linux-4.4.14/arch/arm/mach-imx/
H A Dmach-armadillo5x0.c207 err = gpio_request(USBH2_CS, "USB-H2-CS"); usbh2_init()
209 pr_err("Failed to request the usb host 2 CS gpio\n"); usbh2_init()
215 pr_err("Failed to drive the usb host 2 CS gpio\n"); usbh2_init()
H A Dmach-mx31lilly.c179 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); usbh2_init()
266 mxc_iomux_alloc_pin(MX31_PIN_CS4__CS4, "Ethernet CS"); mx31lilly_board_init()
H A Dmach-mx31lite.c166 gpio_request(IOMUX_TO_GPIO(MX31_PIN_DTR_DCE1), "USBH2 CS"); usbh2_init()
H A Dmach-qong.c192 /* init CS */ qong_init_nand_mtd()
H A Dmx21.h75 /* Memory regions and CS */
H A Dmx35.h84 * Memory regions and CS
H A Dmx3x.h111 * Memory regions and CS
H A Dmx27.h97 /* Memory regions and CS */
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Dcik_ih.c219 * - for gfx, hw shader state (0=PS...5=LS, 6=CS)
220 * ME_ID - 0 = gfx, 1 = first 4 CS pipes, 2 = second 4 CS pipes
H A Damdgpu_gem.c476 just abort and wait for the next CS */ amdgpu_gem_va_update_vm()
483 just abort and wait for the next CS */ amdgpu_gem_va_update_vm()
/linux-4.4.14/drivers/scsi/aic7xxx/
H A Daic7xxx_93cx6.h73 * CS - Chip select
H A Daic7xxx_93cx6.c134 * Clear CS put the chip in the reset state, where it can wait for new commands.
/linux-4.4.14/arch/x86/boot/
H A Dpm.c71 /* CS: code, read/execute, 4 GB, base 0 */ setup_gdt()
/linux-4.4.14/arch/x86/kernel/
H A Dhead_64.S51 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
167 * At this point the CPU runs in 64bit mode CS.L = 1 CS.D = 0,
H A Dmcount_64.S214 movq %rcx, CS(%rsp)
H A Dhead_32.S91 * CS and DS must be 4 GB flat segments, but we don't depend on
726 .ascii " vec %p err %p EIP %p CS %p flg %p\n"
H A Dprocess_64.c100 printk(KERN_DEFAULT "CS: %04x DS: %04x ES: %04x CR0: %016lx\n", cs, ds, __show_regs()
322 * Note that we don't need to do anything for CS and SS, as __switch_to()
H A Dsignal.c101 /* Kernel saves and restores only the CS segment register on signals, restore_sigcontext()
462 /* Set up the CS register to run signal handlers in 64-bit mode, __setup_rt_frame()
H A Dsmp.c92 * 8AP. worked around in hardware - we get explicit CS errors if not
/linux-4.4.14/arch/x86/platform/efi/
H A Defi_stub_32.S26 * 0. The function can only be called in Linux kernel. So CS has been
/linux-4.4.14/arch/arm/mach-ixp4xx/include/mach/
H A Dplatform.h33 * 32MB windows and the CS offset for each region changes based on the
/linux-4.4.14/sound/i2c/
H A Dcs8427.c186 Registers 32-55 window to CS buffer snd_cs8427_init()
187 Inhibit D->E transfers from overwriting first 5 bytes of CS data. snd_cs8427_init()
188 Inhibit D->E transfers (all) of CS data. snd_cs8427_init()
189 Allow E->F transfer of CS data. snd_cs8427_init()
/linux-4.4.14/drivers/memory/
H A Domap-gpmc.c337 return gpmc_ns_to_clk_ticks(time_ns, /* any CS */ 0, GPMC_CD_FCLK); gpmc_ns_to_ticks()
358 return gpmc_clk_ticks_to_ns(ticks, /* any CS */ 0, GPMC_CD_FCLK); gpmc_ticks_to_ns()
608 pr_err("%s: GPMC CS%d: %s %d ns, %d ticks > %d ticks\n", set_gpmc_timing_reg()
617 "GPMC CS%d: %-17s: %3d ticks, %3lu ns (was %3i ticks) %3d ns\n", set_gpmc_timing_reg()
770 pr_info("GPMC CS%d CLK period is %lu ns (div %d)\n", gpmc_cs_set_timings()
987 /* Disable CS while changing base address and size mask */ gpmc_cs_request()
996 /* Enable CS */ gpmc_cs_request()
1013 printk(KERN_ERR "Trying to free non-reserved GPMC CS%d\n", cs); gpmc_cs_free()
1947 dev_err(&pdev->dev, "cannot request GPMC CS %d\n", cs); gpmc_probe_generic_child()
1961 WARN(1, "enable GPMC debug to configure .dts timings for CS%i\n", gpmc_probe_generic_child()
1968 /* CS must be disabled while making changes to gpmc configuration */ gpmc_probe_generic_child()
1972 * FIXME: gpmc_cs_request() will map the CS to an arbitary gpmc_probe_generic_child()
1976 * CS to this location. Once DT migration is complete should gpmc_probe_generic_child()
1981 dev_err(&pdev->dev, "cannot remap GPMC CS %d to %pa\n", gpmc_probe_generic_child()
2007 /* Enable CS region */ gpmc_probe_generic_child()
/linux-4.4.14/drivers/staging/fbtft/
H A Dfb_watterott.c158 /* enable SPI interface by having CS and MOSI low during reset */ init_display()
161 ret = spi_setup(par->spi); /* set CS inactive low */ init_display()
H A Dfb_uc1611.c75 /* Set CS active high */ init_display()
/linux-4.4.14/drivers/atm/
H A Dfore200e.h399 __be32 cells_protocol_errors; /* SAR or CS layer protocol errors */
401 __be32 cspdus_transmitted; /* CS PDUs transmitted */
402 __be32 cspdus_received; /* CS PDUs received */
403 __be32 cspdus_protocol_errors; /* CS layer protocol errors */
416 __be32 cspdus_transmitted; /* CS PDUs transmitted */
417 __be32 cspdus_received; /* CS PDUs received */
418 __be32 cspdus_crc_errors; /* CS PDUs CRC errors */
419 __be32 cspdus_protocol_errors; /* CS layer protocol errors */
/linux-4.4.14/firmware/
H A Dihex2fw.c67 fprintf(stderr, " -j: include records for CS:IP/EIP address\n"); usage()
235 /* These records contain the CS/IP or EIP where execution process_ihex()
/linux-4.4.14/include/uapi/drm/
H A Damdgpu_drm.h291 /** CS status: 0 - CS completed, 1 - CS still busy */
316 /* Delay the page table update till the next CS */
365 /** Handle of resource list associated with CS */
/linux-4.4.14/drivers/video/fbdev/omap/
H A Dsossi.c278 /* CS active low */ sossi_start_transfer()
286 /* CS active low */ sossi_stop_transfer()
335 /* no CS on SOSSI, so ignore cson, csoff, cs_pulsewidth */ sossi_convert_timings()
/linux-4.4.14/drivers/pinctrl/sunxi/
H A Dpinctrl-sun8i-a23.c29 SUNXI_FUNCTION(0x2, "spi1"), /* CS */
131 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
543 SUNXI_FUNCTION(0x2, "spi0"), /* CS */
H A Dpinctrl-sun8i-a33.c91 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
465 SUNXI_FUNCTION(0x2, "spi0"), /* CS */
H A Dpinctrl-sun8i-a83t.c109 SUNXI_FUNCTION(0x3, "spi0")), /* CS */
470 SUNXI_FUNCTION(0x3, "spi1"), /* CS */
/linux-4.4.14/arch/mips/alchemy/devboards/
H A Ddb1300.c56 /* SMSC9210 CS */
60 /* ATA CS */
65 /* NAND CS */
H A Ddb1000.c465 .controller_data = (void *)210, /* for spi_gpio: CS# GPIO210 */
H A Ddb1550.c222 gpio_direction_input(206); /* de-assert NAND CS# */ pb1550_nand_setup()
/linux-4.4.14/arch/mips/ath25/
H A Dar2315_regs.h324 #define AR2315_LBCONF_CS0 0x00000002 /* =1 first CS is low-true */
325 #define AR2315_LBCONF_CS1 0x00000004 /* =1 2nd CS is low-true */
331 #define AR2315_LBCONF_8CS 0x00000100 /* =1 8 bits CS, 0= 16bits */
/linux-4.4.14/drivers/isdn/act2000/
H A Dact2000_isa.h69 /* N/A | N/A | N/A |ROM Hold| ROM CS |ROM CLK | ROM IN |ROM Out */
/linux-4.4.14/drivers/isdn/mISDN/
H A Ddsp_blowfish.c45 * checksumme (CS) for sync (0, 1) and for the last bit:
53 * CS 4(4) 4(3) 4(2) 4(1) 4(0) 5(7) 5(6)
54 * CS 5(5) 5(4) 5(3) 5(2) 5(1) 5(0) 6(7)
55 * CS 6(6) 6(5) 6(4) 6(3) 6(2) 6(1) 6(0)
/linux-4.4.14/drivers/mtd/nand/gpmi-nand/
H A Dgpmi-regs.h52 /* Difference in CS between imx23 and imx28 */
/linux-4.4.14/drivers/media/pci/netup_unidvb/
H A Dnetup_unidvb_spi.c113 /* reset CS */ netup_spi_transfer()
/linux-4.4.14/drivers/mfd/
H A Dcros_ec_spi.c75 * is sent when we want to turn on CS at the start of a transaction.
77 * is sent when we want to turn off CS at the end of a transaction.
108 * Turn off CS, possibly adding a delay to ensure the rising edge terminate_request()
400 * Leave a gap between CS assertion and clocking of data to allow the cros_ec_pkt_xfer_spi()
H A Dmc13xxx-spi.c110 * The MC13783 chip will get corrupted if CS signal is deasserted
/linux-4.4.14/drivers/ata/
H A Dpata_ixp4xx_cf.c8 * must have it chip selects connected to two CS lines
H A Dpata_at91.c164 dev_warn(dev, "maximal SMC CS Pulse value\n"); calc_smc_vals()
242 dev_dbg(dev, "SMC Setup=%u, Pulse=%u, Cycle=%u, CS Pulse=%u\n", set_smc_timing()
/linux-4.4.14/drivers/bus/
H A Dimx-weim.c118 /* get the CS index from this child node's "reg" property. */ weim_timing_setup()
H A Dmvebu-mbus.c660 * The CS is fully enclosed inside the MBus bridge mvebu_mbus_setup_cpu_target_nooverlap()
667 * Beginning of CS overlaps with end of MBus, raise CS mvebu_mbus_setup_cpu_target_nooverlap()
676 * End of CS overlaps with beginning of MBus, shrink mvebu_mbus_setup_cpu_target_nooverlap()
677 * CS size. mvebu_mbus_setup_cpu_target_nooverlap()
770 w->mbus_attr = 0; /* CS address decoding done inside */ mvebu_mbus_dove_setup_cpu_target()
/linux-4.4.14/arch/powerpc/platforms/52xx/
H A Dlite5200.c114 port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */ lite5200_fix_port_config()
H A Dmedia5200.c224 port_config &= ~0x03000000; /* ATA CS is on csb_4/5 */ media5200_setup_arch()
/linux-4.4.14/arch/mips/include/asm/txx9/
H A Djmr3927.h17 /* CS */
/linux-4.4.14/arch/mips/netlogic/xlr/
H A Dplatform-flash.c196 /* Initialize NAND flash at CS 0 */ xlr_flash_init()
/linux-4.4.14/arch/arm64/kvm/
H A Demulate.c39 0xCCCC, /* CS == C set */
/linux-4.4.14/drivers/pinctrl/sh-pfc/
H A Dpfc-r8a7779.c1619 /* CLK, CS, RX, TX */
1628 /* CLK, CS, RX, TX */
1636 /* CLK, CS, RX, TX */
1644 /* CLK, CS, RX, TX */
1652 /* CLK, CS, RX, TX */
1661 /* CLK, CS, RX, TX */
1669 /* CLK, CS, RX, TX */
1808 /* CS */
1815 /* CS */
1822 /* CS */
1829 /* CS */
1836 /* CS */
1843 /* CS */
1850 /* CS */
1857 /* CS */
H A Dpfc-r8a7740.c1692 /* CS */
1699 /* CS */
1706 /* CS */
1713 /* CS */
1720 /* CS */
1727 /* CS */
1734 /* CS */
2191 /* CS, WR, RD, RS */
2286 /* CS, WR, RD, RS */
H A Dpfc-sh73a0.c1474 /* CS */
1481 /* CS */
1488 /* CS */
1495 /* CS */
1502 /* CS */
2036 /* CS, WR, RD, RS */
2126 /* CS, WR, RD, RS */
2134 /* CS, WR, RD, RS */
/linux-4.4.14/drivers/net/ethernet/intel/e1000e/
H A Dnvm.c206 /* Toggle CS to flush commands */ e1000_standby_nvm()
230 /* Pull CS high */ e1000_stop_nvm()
268 /* Clear SK and CS */ e1000_ready_nvm_eeprom()
/linux-4.4.14/drivers/net/ethernet/intel/igb/
H A De1000_nvm.c217 /* Toggle CS to flush commands */ igb_standby_nvm()
241 /* Pull CS high */ e1000_stop_nvm()
280 /* Clear SK and CS */ igb_ready_nvm_eeprom()
/linux-4.4.14/drivers/iio/light/
H A Dcm36651.c152 /* CS initialization */ cm36651_setup_reg()
416 dev_err(&client->dev, "CS integration time write failed\n"); cm36651_write_int_time()
/linux-4.4.14/drivers/net/ethernet/intel/ixgb/
H A Dixgb_ee.c192 /* Set CS */ ixgb_setup_eeprom()
295 /* Toggle the CS line. This in effect tells to EEPROM to actually execute ixgb_wait_eeprom_command()
/linux-4.4.14/drivers/edac/
H A Damd64_edac.h88 * The memory controller for a given node uses its DRAM CS Base and
89 * DRAM CS Mask registers to map an InputAddr to a csrow. See
/linux-4.4.14/drivers/char/
H A Dtoshiba.c132 * For the Portage 610CT and the Tecra 700CS/700CDT emulate the HCI fan function
178 /* Tecra 700CS/CDT */ tosh_emulate_fan()
/linux-4.4.14/include/uapi/linux/usb/
H A Daudio.h102 #define UAC_CONTROL_BIT(CS) (1 << ((CS) - 1))
/linux-4.4.14/arch/blackfin/mach-bf527/boards/
H A Dtll6527m.c186 * outputs used as SPI CS lines for all SPI SLAVE devices on TLL6527v1-0.
188 * used as SPI CS lines, this should be > MAX_BLACKFIN_GPIOS
/linux-4.4.14/drivers/tty/serial/
H A Dicom.h108 u8 cs_length; /* 1F6 CS Load Length */
/linux-4.4.14/drivers/rtc/
H A Drtc-pcf2123.c17 * Please note that the CS is active high, so platform data
H A Drtc-rs5c348.c12 * Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS
H A Drtc-v3020.c106 { 0, GPIOF_OUT_INIT_HIGH, "RTC CS"},
/linux-4.4.14/drivers/s390/cio/
H A Dccwreq.c337 "(CS=%02x, DS=%02x, CHPID=%x.%02x)\n", ccw_request_timeout()
/linux-4.4.14/drivers/video/backlight/
H A Dili9320.c182 * says they should be done as two distinct cycles of the SPI CS line. ili9320_setup_spi()
/linux-4.4.14/drivers/iio/adc/
H A Dad7887.c33 #define AD7887_PM_MODE1 0 /* CS based shutdown */
H A Dad7923.c5 * Copyright 2012 CS Systemes d'Information
H A Dmax1027.c7 * Copyright 2012 CS Systemes d'Information
/linux-4.4.14/drivers/media/pci/cx23885/
H A Dcx23885-417.c332 /* Transition CS/WR to effect write transaction across bus. */ mc417_register_write()
437 /* Bring CS and RD high. */ mc417_register_read()
490 /* Transition CS/WR to effect write transaction across bus. */ mc417_memory_write()
591 /* Bring CS and RD high. */ mc417_memory_read()
H A Dcx23885-cards.c1311 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ cx23885_gpio_setup()
1352 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ cx23885_gpio_setup()
1508 /* GPIO-15-18 cx23417 READY, CS, RD, WR */ cx23885_gpio_setup()
1540 GPIO-11 ~CS out cx23885_gpio_setup()
1557 /* ~RD, ~WR high; ADDR low; ~CS high */ cx23885_gpio_setup()
H A Daltera-ci.c27 * GPIO-11 ~CS out
44 * | TDI | TDO | TCK | RDY# | #RD | #WR | AD_RG | #CS |
/linux-4.4.14/arch/x86/entry/vsyscall/
H A Dvsyscall_64.c132 * No point in checking CS -- the only way to get here is a user mode emulate_vsyscall()
/linux-4.4.14/arch/x86/tools/
H A Dgen-insn-attr-x86.awk89 prefix_num["SEG=CS"] = "INAT_PFX_CS"
/linux-4.4.14/arch/mips/txx9/rbtx4938/
H A Dsetup.c281 /* Mode 1 (High-Active, Shift-Then-Sample), High Avtive CS */ rbtx4938_spi_init()
/linux-4.4.14/arch/powerpc/boot/
H A Dcuboot-pq2.c93 /* If CS is already valid, use the existing flags. update_cs_ranges()
H A D4xx.c192 /* get CS value */ ibm4xx_denali_get_cs()
224 fatal("DDR wrong CS configuration\n"); ibm4xx_denali_fixup_memsize()
/linux-4.4.14/arch/m68k/68000/
H A Dhead.S74 movel #0x00011f07, 0xfffff114 /* CS A1 Mask */
/linux-4.4.14/arch/arm/mach-orion5x/
H A Ddb88f5281-setup.c72 * 512M NOR Flash on Device bus Boot CS
/linux-4.4.14/arch/arm/mach-s3c64xx/
H A Dmach-smartq.c212 /* GPM0 -> CS */
/linux-4.4.14/arch/arm/mach-clps711x/
H A Dboard-autcpu12.c164 { AUTCPU12_DPOT_CS, GPIOF_OUT_INIT_HIGH, "DPOT CS" },
/linux-4.4.14/drivers/gpio/
H A Dgpio-max730x.c25 * - raise CS and assert it again
/linux-4.4.14/sound/soc/intel/common/
H A Dsst-dsp.h72 /* CSR / CS */
/linux-4.4.14/tools/perf/util/intel-pt-decoder/
H A Dgen-insn-attr-x86.awk89 prefix_num["SEG=CS"] = "INAT_PFX_CS"
/linux-4.4.14/drivers/input/misc/
H A Dadxl34x.c381 * transition to register 0x38 from 0x37 or the CS pin adxl34x_irq()
387 * greater than 1.5 MHz to de-assert the CS pin to ensure a adxl34x_irq()
/linux-4.4.14/arch/tile/include/arch/
H A Dmpipe_shm.h353 * resultant checksum if CS bit is asserted. The endianness of the CSUM
361 * byte swap will be visible to Tile software if the CS bit is clear.
/linux-4.4.14/arch/metag/tbx/
H A Dtbipcx.S256 LSLS D1Ar5,D0Re0,#1 /* Test XCBF (MI) & PRIV (CS)? */
286 LSLS D1Ar5,D0Re0,#1 /* Test XCBF (MI) & PRIV (CS)? */
/linux-4.4.14/arch/frv/kernel/
H A Dhead.S138 # consult the SDRAM controller CS address registers
151 # assume the lowest valid CS line to be the SDRAM base and get its address
/linux-4.4.14/drivers/mtd/maps/
H A Dnettel.c197 * Save the CS settings then ensure ROMCS1 and ROMCS2 are off, nettel_init()
/linux-4.4.14/drivers/net/wireless/cw1200/
H A Dcw1200_spi.c387 pr_info("cw1200_wlan_spi: Probe called (CS %d M %d BPW %d CLK %d)\n", cw1200_spi_probe()
/linux-4.4.14/drivers/net/wireless/ath/
H A Dregd_common.h447 {CTRY_SERBIA_MONTENEGRO, ETSI1_WORLD, "CS"},
/linux-4.4.14/drivers/block/paride/
H A Dppc6lnx.c61 #define EEPROM_CS 0x04 // eeprom CS bit
/linux-4.4.14/arch/arm/mach-netx/include/mach/
H A Dnetx-regs.h338 #define NETX_MEMCR_SRAM_CTRL(cs) NETX_MEMCR_REG(0x0 + 4 * (cs)) /* SRAM for CS 0..2 */

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