Searched refs:CP_ME_CNTL (Results 1 – 12 of 12) sorted by relevance
| /linux-4.4.14/drivers/gpu/drm/amd/amdgpu/ |
| D | vi.c | 722 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); in vi_gpu_soft_reset()
723 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); in vi_gpu_soft_reset()
724 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); in vi_gpu_soft_reset()
865 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); in vi_gpu_pci_config_reset()
866 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); in vi_gpu_pci_config_reset()
867 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); in vi_gpu_pci_config_reset()
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| D | gfx_v8_0.c | 3113 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 0); in gfx_v8_0_cp_gfx_enable()
3114 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 0); in gfx_v8_0_cp_gfx_enable()
3115 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 0); in gfx_v8_0_cp_gfx_enable()
3117 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, ME_HALT, 1); in gfx_v8_0_cp_gfx_enable()
3118 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, PFP_HALT, 1); in gfx_v8_0_cp_gfx_enable()
3119 tmp = REG_SET_FIELD(tmp, CP_ME_CNTL, CE_HALT, 1); in gfx_v8_0_cp_gfx_enable()
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| /linux-4.4.14/drivers/gpu/drm/radeon/ |
| D | ni.c | 1470 WREG32(CP_ME_CNTL, 0); in cayman_cp_enable()
1474 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in cayman_cp_enable()
1852 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in cayman_gpu_soft_reset()
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| D | rv770d.h | 335 #define CP_ME_CNTL 0x86D8 macro
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| D | nid.h | 318 #define CP_ME_CNTL 0x86D8 macro
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| D | sid.h | 1027 #define CP_ME_CNTL 0x86D8 macro
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| D | cikd.h | 1110 #define CP_ME_CNTL 0x86D8 macro
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| D | si.c | 3464 WREG32(CP_ME_CNTL, 0); in si_cp_enable()
3468 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in si_cp_enable()
3877 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_soft_reset()
4046 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in si_gpu_pci_config_reset()
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| D | rv770.c | 1081 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); in r700_cp_stop()
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| D | evergreen.c | 3107 WREG32(CP_ME_CNTL, cp_me); in evergreen_cp_start()
3997 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_soft_reset()
4107 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT); in evergreen_gpu_pci_config_reset()
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| D | evergreend.h | 461 #define CP_ME_CNTL 0x86D8 macro
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| D | cik.c | 4281 WREG32(CP_ME_CNTL, 0); in cik_cp_gfx_enable()
4285 WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT)); in cik_cp_gfx_enable()
5360 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_soft_reset()
5564 WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT); in cik_gpu_pci_config_reset()
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