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Searched refs:CP_MEC_CNTL__MEC_ME1_HALT_MASK (Results 1 – 7 of 7) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
Dcik.c1184 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in cik_gpu_soft_reset()
1391 CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in cik_gpu_pci_config_reset()
Dvi.c882 CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in vi_gpu_pci_config_reset()
Dgfx_v7_0.c3060 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v7_0_cp_compute_enable()
5259 WREG32(mmCP_MEC_CNTL, CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK); in gfx_v7_0_soft_reset()
Dgfx_v8_0.c3384 WREG32(mmCP_MEC_CNTL, (CP_MEC_CNTL__MEC_ME1_HALT_MASK | CP_MEC_CNTL__MEC_ME2_HALT_MASK)); in gfx_v8_0_cp_compute_enable()
/linux-4.4.14/drivers/gpu/drm/amd/include/asic_reg/gca/
Dgfx_7_2_sh_mask.h2225 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 macro
Dgfx_8_1_sh_mask.h3293 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 macro
Dgfx_8_0_sh_mask.h2771 #define CP_MEC_CNTL__MEC_ME1_HALT_MASK 0x40000000 macro