Searched refs:CPG_PLL1CR (Results 1 – 2 of 2) sorted by relevance
33 #define CPG_PLL1CR 0x28 macro102 enable_reg += CPG_PLL1CR; in sh73a0_cpg_register_clock()
31 #define CPG_PLL1CR 0x28 macro105 u32 value = clk_readl(cpg->reg + CPG_PLL1CR); in r8a73a4_cpg_register_clock()