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Searched refs:CORE_MOD (Results 1 – 13 of 13) sorted by relevance

/linux-4.4.14/arch/arm/mach-omap2/
Domap_hwmod_2xxx_ipblock_data.c272 .module_offs = CORE_MOD,
290 .module_offs = CORE_MOD,
308 .module_offs = CORE_MOD,
326 .module_offs = CORE_MOD,
345 .module_offs = CORE_MOD,
364 .module_offs = CORE_MOD,
383 .module_offs = CORE_MOD,
402 .module_offs = CORE_MOD,
421 .module_offs = CORE_MOD,
440 .module_offs = CORE_MOD,
[all …]
Domap_hwmod_2430_data.c99 .module_offs = CORE_MOD,
117 .module_offs = CORE_MOD,
137 .module_offs = CORE_MOD,
171 .module_offs = CORE_MOD,
188 .module_offs = CORE_MOD,
225 .module_offs = CORE_MOD,
272 .module_offs = CORE_MOD,
290 .module_offs = CORE_MOD,
308 .module_offs = CORE_MOD,
326 .module_offs = CORE_MOD,
[all …]
Dcm3xxx.c429 omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); in omap3_cm_save_context()
431 omap2_cm_read_mod_reg(CORE_MOD, OMAP3430ES2_CM_FCLKEN3); in omap3_cm_save_context()
445 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN1); in omap3_cm_save_context()
447 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN2); in omap3_cm_save_context()
449 omap2_cm_read_mod_reg(CORE_MOD, CM_ICLKEN3); in omap3_cm_save_context()
471 omap2_cm_read_mod_reg(CORE_MOD, OMAP2_CM_CLKSTCTRL); in omap3_cm_save_context()
486 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE1); in omap3_cm_save_context()
488 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE2); in omap3_cm_save_context()
490 omap2_cm_read_mod_reg(CORE_MOD, CM_AUTOIDLE3); in omap3_cm_save_context()
559 omap2_cm_write_mod_reg(cm_context.core_cm_fclken1, CORE_MOD, in omap3_cm_restore_context()
[all …]
Dpm24xx.c79 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); in omap2_enter_full_retention()
80 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); in omap2_enter_full_retention()
108 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); in omap2_enter_full_retention()
109 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); in omap2_enter_full_retention()
145 omap_prm_clear_mod_irqs(CORE_MOD, PM_WKST1, ~0); in omap2_enter_mpu_retention()
146 omap_prm_clear_mod_irqs(CORE_MOD, OMAP24XX_PM_WKST2, ~0); in omap2_enter_mpu_retention()
Domap_hwmod_2420_data.c113 .module_offs = CORE_MOD,
136 .module_offs = CORE_MOD,
173 .module_offs = CORE_MOD,
203 .module_offs = CORE_MOD,
221 .module_offs = CORE_MOD,
253 .module_offs = CORE_MOD,
267 .module_offs = CORE_MOD,
Dcm2xxx.c334 f1 = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); in omap2xxx_cm_fclks_active()
335 f2 = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); in omap2xxx_cm_fclks_active()
345 l = omap2_cm_read_mod_reg(CORE_MOD, CM_FCLKEN1); in omap2xxx_cm_mpu_retention_allowed()
351 l = omap2_cm_read_mod_reg(CORE_MOD, OMAP24XX_CM_FCLKEN2); in omap2xxx_cm_mpu_retention_allowed()
380 tmp = omap2_cm_read_mod_reg(CORE_MOD, CM_CLKSEL1) & in omap2xxx_cm_set_mod_dividers()
382 omap2_cm_write_mod_reg(core | tmp, CORE_MOD, CM_CLKSEL1); in omap2xxx_cm_set_mod_dividers()
Domap_hwmod_3xxx_data.c375 .module_offs = CORE_MOD,
394 .module_offs = CORE_MOD,
495 .module_offs = CORE_MOD,
514 .module_offs = CORE_MOD,
606 .module_offs = CORE_MOD,
812 .module_offs = CORE_MOD,
837 .module_offs = CORE_MOD,
873 .module_offs = CORE_MOD,
1105 .module_offs = CORE_MOD,
1165 .module_offs = CORE_MOD,
[all …]
Dprm3xxx.c279 CORE_MOD, OMAP2_RM_RSTCTRL); in omap3_prm_reset_modem()
280 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP2_RM_RSTCTRL); in omap3_prm_reset_modem()
353 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430_PM_IVAGRPSEL1); in omap3_prm_init_pm()
354 omap2_prm_write_mod_reg(0, CORE_MOD, OMAP3430ES2_PM_IVAGRPSEL3); in omap3_prm_init_pm()
361 omap2_prm_write_mod_reg(0xffffffff, CORE_MOD, OMAP2_RM_RSTST); in omap3_prm_init_pm()
Dpowerdomains3xxx_data.c100 .prcm_offs = CORE_MOD,
117 .prcm_offs = CORE_MOD,
139 .prcm_offs = CORE_MOD,
Dpowerdomains2xxx_data.c61 .prcm_offs = CORE_MOD,
Dpm34xx.c157 c += omap_prm_clear_mod_irqs(CORE_MOD, 1, ~0); in _prcm_int_handle_wakeup()
160 c += omap_prm_clear_mod_irqs(CORE_MOD, 3, ~0); in _prcm_int_handle_wakeup()
Dprcm-common.h27 #define CORE_MOD 0x200 macro
Dsleep34xx.S43 #define PM_PREPWSTST_CORE_P OMAP3430_PRM_BASE + CORE_MOD +\
46 #define CM_IDLEST1_CORE_V OMAP34XX_CM_REGADDR(CORE_MOD, CM_IDLEST1)