| /linux-4.4.14/arch/c6x/kernel/ |
| H A D | head.S | 46 CLR .S2 B2,0,1,B2
49 CLR .S2 B2,0,1,B2
52 CLR .S2 B2,0,1,B2
55 CLR .S2 B2,0,1,B2
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| H A D | entry.S | 32 CLR .S2 reg,0,0,reg
523 CLR .S2 B1,10,10,B1
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| /linux-4.4.14/drivers/clk/imx/ |
| H A D | clk-pfd.c | 27 * register has SET, CLR and TOG registers at offset 0x4 0x8 and 0xc.
38 #define CLR 0x8 macro
45 writel_relaxed(1 << ((pfd->idx + 1) * 8 - 1), pfd->reg + CLR); clk_pfd_enable()
105 writel_relaxed(0x3f << (pfd->idx * 8), pfd->reg + CLR); clk_pfd_set_rate()
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| /linux-4.4.14/include/linux/platform_data/ |
| H A D | ad5449.h | 32 * @hardware_clear_to_midscale: Whether asserting the hardware CLR pin sets the
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| /linux-4.4.14/drivers/clk/mxs/ |
| H A D | clk-pll.c | 53 writel_relaxed(1 << pll->power, pll->base + CLR); clk_pll_unprepare()
60 writel_relaxed(1 << 31, pll->base + CLR); clk_pll_enable()
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| H A D | clk.h | 21 #define CLR 0x8 macro
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| H A D | clk-imx23.c | 58 writel_relaxed(1 << BP_CLKSEQ_BYPASS_SAIF, CLKSEQ + CLR); clk_misc_init()
69 writel_relaxed(1 << BP_CLKSEQ_BYPASS_SSP, CLKSEQ + CLR); clk_misc_init()
75 writel_relaxed(0x3f << BP_FRAC_IOFRAC, FRAC + CLR); clk_misc_init()
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| H A D | clk-imx28.c | 79 writel_relaxed(0x3 << BP_SAIF_CLKMUX, DIGCTRL + CLR); mxs_saif_clkmux_select()
96 writel_relaxed(0x3 << BP_CLKSEQ_BYPASS_SAIF0, CLKSEQ + CLR); clk_misc_init()
116 writel_relaxed(0xf << BP_CLKSEQ_BYPASS_SSP0, CLKSEQ + CLR); clk_misc_init()
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| H A D | clk-ref.c | 41 writel_relaxed(1 << ((ref->idx + 1) * 8 - 1), ref->reg + CLR); clk_ref_enable()
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| /linux-4.4.14/arch/arm/boot/compressed/ |
| H A D | head-sharpsl.S | 131 orr r3, r3, #0x0a @ SET CLR + FLWP
135 bic r3, r3, #2 @ CLR CLE
140 bic r3, r3, #4 @ CLR ALE
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| /linux-4.4.14/drivers/pinctrl/freescale/ |
| H A D | pinctrl-mxs.h | 19 #define CLR 0x8 macro
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| H A D | pinctrl-mxs.c | 215 writel(0x3 << shift, reg + CLR); mxs_pinctrl_set_mux()
283 writel(0x3 << shift, reg + CLR); mxs_pinconf_group_set()
293 writel(1 << shift, reg + CLR); mxs_pinconf_group_set()
304 writel(1 << shift, reg + CLR); mxs_pinconf_group_set()
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| /linux-4.4.14/drivers/pwm/ |
| H A D | pwm-mxs.c | 25 #define CLR 0x8 macro
119 writel(1 << pwm->hwpwm, mxs->base + PWM_CTRL + CLR); mxs_pwm_disable()
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| /linux-4.4.14/arch/mips/include/asm/mach-pmcs-msp71xx/ |
| H A D | msp_gpio_macros.h | 212 * - In output mode (ENABLED flag set), check the CLR bit msp_gpio_pin_get()
244 * We have to read the CLR bit. msp_gpio_pin_set()
245 * If set, we write the CLR bit. msp_gpio_pin_set()
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| /linux-4.4.14/sound/soc/rockchip/ |
| H A D | rockchip_i2s.h | 195 * CLR
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| /linux-4.4.14/drivers/tty/serial/ |
| H A D | sirfsoc_uart.h | 419 /* for SiRFatlas7, there are SET/CLR for UART_INT_EN */
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| /linux-4.4.14/drivers/rtc/ |
| H A D | rtc-stmp3xxx.c | 82 * to configure the watchdog. Locking is not needed because accessing SET/CLR
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| /linux-4.4.14/arch/c6x/lib/ |
| H A D | csum_64plus.S | 418 CLR .S1 A4,16,31,A4
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| /linux-4.4.14/drivers/watchdog/ |
| H A D | at32ap700x_wdt.c | 126 wdt_writel(wdt, CLR, 0x42); at32_wdt_pat()
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| /linux-4.4.14/drivers/media/dvb-frontends/ |
| H A D | zl10036.c | 181 * 13[0x28]: PD | BR4 | BR3 | BR2 | BR1 | BR0 | CLR | TL
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| H A D | cx24116.c | 1016 * CLR :SET cx24116_send_diseqc_msg()
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| H A D | cx24117.c | 1074 * CLR :SET cx24117_send_diseqc_msg()
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| /linux-4.4.14/drivers/net/wireless/iwlegacy/ |
| H A D | csr.h | 125 * SET/CLR registers set/clear bit(s) if "1" is written.
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| /linux-4.4.14/drivers/ata/ |
| H A D | sata_sil24.c | 163 /* PORT_IRQ_STAT/ENABLE_SET/CLR */
187 /* ENABLE_SET/CLR specific, intr steering - 2 bit field */
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| /linux-4.4.14/arch/cris/arch-v10/drivers/ |
| H A D | sync_serial.c | 108 char data_avail_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
109 char transmitter_ready_bit; /* In R_IRQ_MASK1_RD/SET/CLR */
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| /linux-4.4.14/drivers/scsi/sym53c8xx_2/ |
| H A D | sym_defs.h | 518 * CLR (flags {|.. })
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| /linux-4.4.14/drivers/net/wireless/iwlwifi/ |
| H A D | iwl-csr.h | 125 * SET/CLR registers set/clear bit(s) if "1" is written.
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| /linux-4.4.14/drivers/video/fbdev/ |
| H A D | imsttfb.c | 52 CLR = 6, /* 0x18 */ enumerator in enum:__anon11126
1017 write_reg_le32(par->dc_regs, CLR, bgc); imsttfb_fillrect()
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| /linux-4.4.14/drivers/scsi/ |
| H A D | ncr53c8xx.h | 1035 ** CLR (flags {|.. })
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| /linux-4.4.14/drivers/net/ieee802154/ |
| H A D | mrf24j40.c | 746 devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */ mrf24j40_handle_rx_read_buf_unlock()
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| /linux-4.4.14/fs/fscache/ |
| H A D | object.c | 107 static WAIT_STATE(WAIT_FOR_CLEARANCE, "?CLR",
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| /linux-4.4.14/virt/kvm/arm/ |
| H A D | vgic-v3-emul.c | 13 * writes to the GICD_{SET,CLR}SPI_* registers. TYPER.MBIS is reported as 0.
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| /linux-4.4.14/drivers/clk/sirf/ |
| H A D | clk-atlas7.c | 1252 /*once timeout, undo idlereq by CLR*/ unit_clk_disable()
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| /linux-4.4.14/drivers/net/ethernet/broadcom/bnx2x/ |
| H A D | bnx2x_reg.h | 1684 (#SET; #CLR; or #FLOAT) for this bit was a #FLOAT. (reset value 0xff).
1685 [23-20] CLR port 1; 19-16] CLR port 0; When any of these bits is written
1687 these bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for
1688 this bit was a #CLR. (reset value 0). [15-12] SET port 1; 11-8] port 0;
1691 bits will be a '1' if that last command (#SET; #CLR; or #FLOAT) for this
1841 bit was a #FLOAT. (reset value 0xff). [23-16] CLR When any of these bits
1843 value of these bits will be a '1' if that last command (#SET; #CLR; or
1844 #FLOAT) for this bit was a #CLR. (reset value 0). [15-8] SET When any of
1847 '1' if that last command (#SET; #CLR; or #FLOAT) for this bit was a #SET.
1857 the SET and CLR fields; it is controlled by the Main Power SM; the FLOAT
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| H A D | bnx2x_main.c | 2120 /* clear FLOAT and set CLR */ bnx2x_set_gpio()
2169 /* set CLR */ bnx2x_set_mult_gpio()
2223 /* clear SET and set CLR */ bnx2x_set_gpio_int()
2232 /* clear CLR and set SET */ bnx2x_set_gpio_int()
2264 /* clear FLOAT and set CLR */ bnx2x_set_spio()
9219 * Force both transactions with CLR bit bnx2x_func_wait_started()
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| /linux-4.4.14/drivers/scsi/megaraid/ |
| H A D | megaraid_sas_base.c | 3475 * Set the CLR bit in inbound doorbell megasas_transition_to_ready()
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