Searched refs:CLK_SOURCE_CSITE (Results 1 – 4 of 4) sorted by relevance
106 #define CLK_SOURCE_CSITE 0x1d4 macro960 readl(clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_suspend()961 writel(3<<30, clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_suspend()1010 clk_base + CLK_SOURCE_CSITE); in tegra20_cpu_clock_resume()
142 #define CLK_SOURCE_CSITE 0x1d4 macro1249 readl(clk_base + CLK_SOURCE_CSITE); in tegra114_cpu_clock_suspend()1250 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); in tegra114_cpu_clock_suspend()1261 clk_base + CLK_SOURCE_CSITE); in tegra114_cpu_clock_resume()
39 #define CLK_SOURCE_CSITE 0x1d4 macro1327 readl(clk_base + CLK_SOURCE_CSITE); in tegra124_cpu_clock_suspend()1328 writel(3 << 30, clk_base + CLK_SOURCE_CSITE); in tegra124_cpu_clock_suspend()1339 clk_base + CLK_SOURCE_CSITE); in tegra124_cpu_clock_resume()
62 #define CLK_SOURCE_CSITE 0x1d4 macro495 …MUX_FLAGS("csite", mux_pllp_pllc_pllm_clkm, CLK_SOURCE_CSITE, 73, TEGRA_PERIPH_ON_APB, tegra_clk_c…