Searched refs:CLK_RESET_CCLK_DIVIDER (Results 1 – 4 of 4) sorted by relevance
| /linux-4.4.14/arch/arm/mach-tegra/ |
| D | sleep.S | 38 #define CLK_RESET_CCLK_DIVIDER 0x24 macro
158 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
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| D | sleep-tegra20.S | 41 #define CLK_RESET_CCLK_DIVIDER 0x24 macro
351 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
439 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
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| D | sleep-tegra30.S | 56 #define CLK_RESET_CCLK_DIVIDER 0x24 macro
333 str r1, [r0, #CLK_RESET_CCLK_DIVIDER]
622 str r0, [r5, #CLK_RESET_CCLK_DIVIDER]
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| /linux-4.4.14/drivers/clk/tegra/ |
| D | clk-tegra30.c | 146 #define CLK_RESET_CCLK_DIVIDER 0x24 macro
1280 readl(clk_base + CLK_RESET_CCLK_DIVIDER); in tegra30_cpu_clock_suspend()
1315 clk_base + CLK_RESET_CCLK_DIVIDER); in tegra30_cpu_clock_resume()
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