Searched refs:CLK_PCLK_DDR_PHY0 (Results 1 - 8 of 8) sorted by relevance

/linux-4.4.14/arch/arm/boot/dts/include/dt-bindings/clock/
H A Dexynos5433.h379 #define CLK_PCLK_DDR_PHY0 179 macro
/linux-4.4.14/arch/cris/boot/dts/include/dt-bindings/clock/
H A Dexynos5433.h379 #define CLK_PCLK_DDR_PHY0 179 macro
/linux-4.4.14/include/dt-bindings/clock/
H A Dexynos5433.h379 #define CLK_PCLK_DDR_PHY0 179 macro
/linux-4.4.14/arch/metag/boot/dts/include/dt-bindings/clock/
H A Dexynos5433.h379 #define CLK_PCLK_DDR_PHY0 179 macro
/linux-4.4.14/arch/mips/boot/dts/include/dt-bindings/clock/
H A Dexynos5433.h379 #define CLK_PCLK_DDR_PHY0 179 macro
/linux-4.4.14/arch/powerpc/boot/dts/include/dt-bindings/clock/
H A Dexynos5433.h379 #define CLK_PCLK_DDR_PHY0 179 macro
/linux-4.4.14/arch/arm64/boot/dts/include/dt-bindings/clock/
H A Dexynos5433.h379 #define CLK_PCLK_DDR_PHY0 179 macro
/linux-4.4.14/drivers/clk/samsung/
H A Dclk-exynos5433.c1477 GATE(CLK_PCLK_DDR_PHY0, "pclk_ddr_phy0", "div_aclk_mif_133",

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