Searched refs:CLK_ENABLE_ON_INIT (Results 1 - 22 of 22) sorted by relevance

/linux-4.4.14/arch/sh/kernel/cpu/
H A Dclock-cpg.c9 .flags = CLK_ENABLE_ON_INIT,
15 .flags = CLK_ENABLE_ON_INIT,
20 .flags = CLK_ENABLE_ON_INIT,
25 .flags = CLK_ENABLE_ON_INIT,
/linux-4.4.14/arch/sh/kernel/cpu/sh4a/
H A Dclock-sh7723.c75 .flags = CLK_ENABLE_ON_INIT,
97 .flags = CLK_ENABLE_ON_INIT,
127 [DIV4_I] = DIV4(FRQCR, 20, 0x0dbf, CLK_ENABLE_ON_INIT),
128 [DIV4_U] = DIV4(FRQCR, 16, 0x0dbf, CLK_ENABLE_ON_INIT),
129 [DIV4_SH] = DIV4(FRQCR, 12, 0x0dbf, CLK_ENABLE_ON_INIT),
130 [DIV4_B] = DIV4(FRQCR, 8, 0x0dbf, CLK_ENABLE_ON_INIT),
131 [DIV4_B3] = DIV4(FRQCR, 4, 0x0db4, CLK_ENABLE_ON_INIT),
155 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
156 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
157 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
158 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
159 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
160 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
161 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
163 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
190 [HWBLK_ICB] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR2, 21, CLK_ENABLE_ON_INIT),
H A Dclock-sh7343.c71 .flags = CLK_ENABLE_ON_INIT,
90 .flags = CLK_ENABLE_ON_INIT,
121 [DIV4_I] = DIV4(FRQCR, 20, 0x1fff, CLK_ENABLE_ON_INIT),
122 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
123 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
124 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
125 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
151 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
152 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
153 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
154 [MSTP028] = MSTP(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
155 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
188 [MSTP206] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 6, CLK_ENABLE_ON_INIT),
192 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
193 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
H A Dclock-sh7366.c71 .flags = CLK_ENABLE_ON_INIT,
93 .flags = CLK_ENABLE_ON_INIT,
124 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
125 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
126 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
127 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
154 [MSTP031] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
155 [MSTP030] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
156 [MSTP029] = MSTP(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
157 [MSTP028] = MSTP(&div4_clks[DIV4_SH], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
158 [MSTP026] = MSTP(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
186 [MSTP207] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 7, CLK_ENABLE_ON_INIT),
190 [MSTP202] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 2, CLK_ENABLE_ON_INIT),
191 [MSTP201] = MSTP(&div4_clks[DIV4_B], MSTPCR2, 1, CLK_ENABLE_ON_INIT),
H A Dclock-sh7724.c80 .flags = CLK_ENABLE_ON_INIT,
99 .flags = CLK_ENABLE_ON_INIT,
166 [DIV4_I] = DIV4(FRQCRA, 20, 0x2f7d, CLK_ENABLE_ON_INIT),
167 [DIV4_SH] = DIV4(FRQCRA, 12, 0x2f7c, CLK_ENABLE_ON_INIT),
168 [DIV4_B] = DIV4(FRQCRA, 8, 0x2f7c, CLK_ENABLE_ON_INIT),
170 [DIV4_M1] = DIV4(FRQCRB, 4, 0x2f7c, CLK_ENABLE_ON_INIT),
206 [DIV6_S] = SH_CLK_DIV6_EXT(SPUCLKCR, CLK_ENABLE_ON_INIT,
215 [HWBLK_TLB] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 31, CLK_ENABLE_ON_INIT),
216 [HWBLK_IC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 30, CLK_ENABLE_ON_INIT),
217 [HWBLK_OC] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 29, CLK_ENABLE_ON_INIT),
218 [HWBLK_RSMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
219 [HWBLK_ILMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 27, CLK_ENABLE_ON_INIT),
220 [HWBLK_L2C] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
221 [HWBLK_FPU] = SH_CLK_MSTP32(&div4_clks[DIV4_I], MSTPCR0, 24, CLK_ENABLE_ON_INIT),
222 [HWBLK_INTC] = SH_CLK_MSTP32(&div4_clks[DIV4_P], MSTPCR0, 22, CLK_ENABLE_ON_INIT),
224 [HWBLK_SHYWAY] = SH_CLK_MSTP32(&div4_clks[DIV4_SH], MSTPCR0, 20, CLK_ENABLE_ON_INIT),
H A Dclock-shx3.c42 .flags = CLK_ENABLE_ON_INIT,
70 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
71 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
72 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
73 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
H A Dclock-sh7785.c46 .flags = CLK_ENABLE_ON_INIT,
76 [DIV4_DDR] = DIV4(12, 0x000c, CLK_ENABLE_ON_INIT),
77 [DIV4_B] = DIV4(16, 0x0fe0, CLK_ENABLE_ON_INIT),
78 [DIV4_SH] = DIV4(20, 0x000c, CLK_ENABLE_ON_INIT),
79 [DIV4_U] = DIV4(24, 0x000c, CLK_ENABLE_ON_INIT),
80 [DIV4_I] = DIV4(28, 0x000e, CLK_ENABLE_ON_INIT),
H A Dclock-sh7722.c74 .flags = CLK_ENABLE_ON_INIT,
96 .flags = CLK_ENABLE_ON_INIT,
126 [DIV4_I] = DIV4(FRQCR, 20, 0x1fef, CLK_ENABLE_ON_INIT),
127 [DIV4_U] = DIV4(FRQCR, 16, 0x1fff, CLK_ENABLE_ON_INIT),
128 [DIV4_SH] = DIV4(FRQCR, 12, 0x1fff, CLK_ENABLE_ON_INIT),
129 [DIV4_B] = DIV4(FRQCR, 8, 0x1fff, CLK_ENABLE_ON_INIT),
130 [DIV4_B3] = DIV4(FRQCR, 4, 0x1fff, CLK_ENABLE_ON_INIT),
154 [HWBLK_URAM] = SH_CLK_MSTP32(&div4_clks[DIV4_U], MSTPCR0, 28, CLK_ENABLE_ON_INIT),
155 [HWBLK_XYMEM] = SH_CLK_MSTP32(&div4_clks[DIV4_B], MSTPCR0, 26, CLK_ENABLE_ON_INIT),
H A Dclock-sh7757.c43 .flags = CLK_ENABLE_ON_INIT,
73 [DIV4_P] = DIV4(0, 0x2800, CLK_ENABLE_ON_INIT),
74 [DIV4_SH] = DIV4(12, 0x00a0, CLK_ENABLE_ON_INIT),
75 [DIV4_I] = DIV4(20, 0x0004, CLK_ENABLE_ON_INIT),
H A Dclock-sh7786.c48 .flags = CLK_ENABLE_ON_INIT,
76 [DIV4_DDR] = DIV4(12, 0x0002, CLK_ENABLE_ON_INIT),
77 [DIV4_B] = DIV4(16, 0x0360, CLK_ENABLE_ON_INIT),
78 [DIV4_SH] = DIV4(20, 0x0002, CLK_ENABLE_ON_INIT),
79 [DIV4_I] = DIV4(28, 0x0006, CLK_ENABLE_ON_INIT),
H A Dclock-sh7734.c48 .flags = CLK_ENABLE_ON_INIT,
76 [DIV4_I] = DIV4(FRQMR1, 28, 0x0003, CLK_ENABLE_ON_INIT),
77 [DIV4_S] = DIV4(FRQMR1, 20, 0x000C, CLK_ENABLE_ON_INIT),
78 [DIV4_B] = DIV4(FRQMR1, 16, 0x0140, CLK_ENABLE_ON_INIT),
79 [DIV4_M] = DIV4(FRQMR1, 12, 0x0004, CLK_ENABLE_ON_INIT),
80 [DIV4_S1] = DIV4(FRQMR1, 4, 0x0030, CLK_ENABLE_ON_INIT),
81 [DIV4_P] = DIV4(FRQMR1, 0, 0x0140, CLK_ENABLE_ON_INIT),
H A Dclock-sh7763.c82 .flags = CLK_ENABLE_ON_INIT,
H A Dclock-sh7780.c88 .flags = CLK_ENABLE_ON_INIT,
/linux-4.4.14/drivers/clk/shmobile/
H A Dclk-r8a7740.c32 #define CLK_ENABLE_ON_INIT BIT(0) macro
42 { "i", CPG_FRQCRA, 20, CLK_ENABLE_ON_INIT },
43 { "zg", CPG_FRQCRA, 16, CLK_ENABLE_ON_INIT },
44 { "b", CPG_FRQCRA, 8, CLK_ENABLE_ON_INIT },
45 { "m1", CPG_FRQCRA, 4, CLK_ENABLE_ON_INIT },
H A Dclk-r8a73a4.c36 #define CLK_ENABLE_ON_INIT BIT(0) macro
H A Dclk-sh73a0.c40 #define CLK_ENABLE_ON_INIT BIT(0) macro
/linux-4.4.14/arch/sh/kernel/cpu/sh2a/
H A Dclock-sh7269.c53 .flags = CLK_ENABLE_ON_INIT,
68 .flags = CLK_ENABLE_ON_INIT,
83 .flags = CLK_ENABLE_ON_INIT,
114 | CLK_ENABLE_ON_INIT),
116 | CLK_ENABLE_ON_INIT),
H A Dclock-sh7264.c57 .flags = CLK_ENABLE_ON_INIT,
86 | CLK_ENABLE_ON_INIT),
/linux-4.4.14/arch/sh/kernel/cpu/sh4/
H A Dclock-sh4-202.c49 .flags = CLK_ENABLE_ON_INIT,
64 .flags = CLK_ENABLE_ON_INIT,
140 .flags = CLK_ENABLE_ON_INIT,
/linux-4.4.14/drivers/sh/clk/
H A Dcpg.c358 * now assume internal parent comes with CLK_ENABLE_ON_INIT set, sh_clk_div4_set_parent()
359 * no CLK_ENABLE_ON_INIT means external clock... sh_clk_div4_set_parent()
362 if (parent->flags & CLK_ENABLE_ON_INIT) sh_clk_div4_set_parent()
H A Dcore.c466 if (clkp->flags & CLK_ENABLE_ON_INIT) clk_enable_init_clocks()
/linux-4.4.14/include/linux/
H A Dsh_clk.h67 #define CLK_ENABLE_ON_INIT BIT(0) macro

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