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Searched refs:CLKGEN_FIELD (Results 1 – 3 of 3) sorted by relevance

/linux-4.4.14/drivers/clk/st/
Dclkgen-fsyn.c167 .npda = CLKGEN_FIELD(0x0, 0x1, 14),
168 .nsb = { CLKGEN_FIELD(0x0, 0x1, 10),
169 CLKGEN_FIELD(0x0, 0x1, 11),
170 CLKGEN_FIELD(0x0, 0x1, 12),
171 CLKGEN_FIELD(0x0, 0x1, 13) },
173 .nsdiv = { CLKGEN_FIELD(0x0, 0x1, 18),
174 CLKGEN_FIELD(0x0, 0x1, 19),
175 CLKGEN_FIELD(0x0, 0x1, 20),
176 CLKGEN_FIELD(0x0, 0x1, 21) },
177 .mdiv = { CLKGEN_FIELD(0x4, 0x1f, 0),
[all …]
Dclkgen-pll.c81 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
82 .pdn_ctrl = CLKGEN_FIELD(0x10, 0x1, 0),
83 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
84 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL1600_MASK, 0),
85 .ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
90 .pdn_status = CLKGEN_FIELD(0x0, 0x1, 19),
91 .pdn_ctrl = CLKGEN_FIELD(0xC, 0x1, 1),
92 .locked_status = CLKGEN_FIELD(0x0, 0x1, 31),
93 .mdiv = CLKGEN_FIELD(0x0, C65_MDIV_PLL800_MASK, 0),
94 .ndiv = CLKGEN_FIELD(0x0, C65_NDIV_MASK, 8),
[all …]
Dclkgen.h37 #define CLKGEN_FIELD(_offset, _mask, _shift) { \ macro