| H A D | bnx2x_link.c | 209 #define CL22_WR_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ macro
3309 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_set_aer_mmd()
3726 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_restart_AN_KR()
3781 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_enable_AN_KR()
3842 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_enable_AN_KR()
3912 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_set_10G_KR()
4097 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_set_20G_force_KR2()
4135 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_set_20G_force_KR2()
4624 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_warpcore_link_reset()
4673 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_set_warpcore_loopback()
4892 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_master_ln()
4910 CL22_WR_OVER_CL45(bp, phy, bnx2x_reset_unicore()
4959 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_swap_lanes()
4966 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_swap_lanes()
4972 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_swap_lanes()
4978 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_swap_lanes()
4999 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_parallel_detection()
5009 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_parallel_detection()
5023 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_parallel_detection()
5029 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_parallel_detection()
5057 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5074 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5092 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5099 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5105 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5124 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5135 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5157 CL22_WR_OVER_CL45(bp, phy, bnx2x_program_serdes()
5184 CL22_WR_OVER_CL45(bp, phy, bnx2x_program_serdes()
5201 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_brcm_cl37_advertisement()
5205 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_brcm_cl37_advertisement()
5218 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_ieee_aneg_advertisement()
5226 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_ieee_aneg_advertisement()
5247 CL22_WR_OVER_CL45(bp, phy, bnx2x_restart_autoneg()
5262 CL22_WR_OVER_CL45(bp, phy, bnx2x_restart_autoneg()
5289 CL22_WR_OVER_CL45(bp, phy, bnx2x_initialize_sgmii_process()
5330 CL22_WR_OVER_CL45(bp, phy, bnx2x_initialize_sgmii_process()
5467 CL22_WR_OVER_CL45(bp, phy, bnx2x_check_fallback_to_cl37()
5511 CL22_WR_OVER_CL45(bp, phy, bnx2x_check_fallback_to_cl37()
5855 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_gmii_tx_driver()
5918 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_preemphasis()
5926 CL22_WR_OVER_CL45(bp, phy, bnx2x_set_preemphasis()
13748 CL22_WR_OVER_CL45(bp, phy, MDIO_REG_BANK_AER_BLOCK, bnx2x_check_kr2_wa()
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