| H A D | bnx2x_link.c | 215 #define CL22_RD_OVER_CL45(_bp, _phy, _bank, _addr, _val) \ macro
4887 CL22_RD_OVER_CL45(bp, phy, bnx2x_set_master_ln()
4905 CL22_RD_OVER_CL45(bp, phy, bnx2x_reset_unicore()
4923 CL22_RD_OVER_CL45(bp, phy, bnx2x_reset_unicore()
4989 CL22_RD_OVER_CL45(bp, phy, bnx2x_set_parallel_detection()
5014 CL22_RD_OVER_CL45(bp, phy, bnx2x_set_parallel_detection()
5046 CL22_RD_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5063 CL22_RD_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5079 CL22_RD_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5113 CL22_RD_OVER_CL45(bp, phy, bnx2x_set_autoneg()
5149 CL22_RD_OVER_CL45(bp, phy, bnx2x_program_serdes()
5164 CL22_RD_OVER_CL45(bp, phy, bnx2x_program_serdes()
5221 CL22_RD_OVER_CL45(bp, phy, bnx2x_set_ieee_aneg_advertisement()
5242 CL22_RD_OVER_CL45(bp, phy, bnx2x_restart_autoneg()
5255 CL22_RD_OVER_CL45(bp, phy, bnx2x_restart_autoneg()
5280 CL22_RD_OVER_CL45(bp, phy, bnx2x_initialize_sgmii_process()
5299 CL22_RD_OVER_CL45(bp, phy, bnx2x_initialize_sgmii_process()
5350 CL22_RD_OVER_CL45(bp, phy, bnx2x_direct_parallel_detect_used()
5354 CL22_RD_OVER_CL45(bp, phy, bnx2x_direct_parallel_detect_used()
5364 CL22_RD_OVER_CL45(bp, phy, bnx2x_direct_parallel_detect_used()
5392 CL22_RD_OVER_CL45(bp, phy, bnx2x_update_adv_fc()
5396 CL22_RD_OVER_CL45(bp, phy, bnx2x_update_adv_fc()
5406 CL22_RD_OVER_CL45(bp, phy, bnx2x_update_adv_fc()
5410 CL22_RD_OVER_CL45(bp, phy, bnx2x_update_adv_fc()
5459 CL22_RD_OVER_CL45(bp, phy, bnx2x_check_fallback_to_cl37()
5474 CL22_RD_OVER_CL45(bp, phy, bnx2x_check_fallback_to_cl37()
5490 CL22_RD_OVER_CL45(bp, phy, bnx2x_check_fallback_to_cl37()
5634 CL22_RD_OVER_CL45(bp, phy, bnx2x_link_settings_status()
5671 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_CL73_IEEEB1, bnx2x_link_settings_status()
5682 CL22_RD_OVER_CL45(bp, phy, MDIO_REG_BANK_OVER_1G, bnx2x_link_settings_status()
5832 CL22_RD_OVER_CL45(bp, phy, bnx2x_set_gmii_tx_driver()
5846 CL22_RD_OVER_CL45(bp, phy, bnx2x_set_gmii_tx_driver()
6491 CL22_RD_OVER_CL45(bp, int_phy, bnx2x_test_link()
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