Searched refs:CG_SPLL_FUNC_CNTL_2 (Results 1 - 16 of 16) sorted by relevance

/linux-4.4.14/drivers/gpu/drm/radeon/
H A Drv740d.h34 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Drv730d.h37 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Drv740_dpm.c292 RREG32(CG_SPLL_FUNC_CNTL_2); rv740_read_clock_registers()
H A Drv770.c1139 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); rv770_set_clk_bypass_mode()
1142 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); rv770_set_clk_bypass_mode()
1151 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); rv770_set_clk_bypass_mode()
H A Drv730_dpm.c205 RREG32(CG_SPLL_FUNC_CNTL_2); rv730_read_clock_registers()
H A Drv770d.h100 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dnid.h547 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dsi.c3992 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); si_set_clk_bypass_mode()
3994 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); si_set_clk_bypass_mode()
4002 tmp = RREG32(CG_SPLL_FUNC_CNTL_2); si_set_clk_bypass_mode()
4004 WREG32(CG_SPLL_FUNC_CNTL_2, tmp); si_set_clk_bypass_mode()
H A Dsid.h94 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dcikd.h259 #define CG_SPLL_FUNC_CNTL_2 0xC0500144 macro
H A Drv770_dpm.c1524 RREG32(CG_SPLL_FUNC_CNTL_2); rv770_read_clock_registers()
H A Devergreend.h82 #define CG_SPLL_FUNC_CNTL_2 0x604 macro
H A Dci_dpm.c1847 RREG32_SMC(CG_SPLL_FUNC_CNTL_2); ci_read_clock_registers()
H A Dni_dpm.c1184 ni_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); ni_read_clock_registers()
H A Dsi_dpm.c3585 si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2); si_read_clock_registers()
/linux-4.4.14/drivers/gpu/drm/amd/amdgpu/
H A Dci_dpm.c6397 dev_info(adev->dev, " CG_SPLL_FUNC_CNTL_2=0x%08X\n", ci_dpm_print_status()

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