Searched refs:CDCLK_CTL (Results 1 – 2 of 2) sorted by relevance
5524 current_freq = I915_READ(CDCLK_CTL) & CDCLK_FREQ_DECIMAL_MASK; in broxton_set_cdclk()5556 val = I915_READ(CDCLK_CTL); in broxton_set_cdclk()5570 I915_WRITE(CDCLK_CTL, val); in broxton_set_cdclk()5686 val = I915_READ(CDCLK_CTL); in skl_dpll0_enable()5697 I915_WRITE(CDCLK_CTL, val); in skl_dpll0_enable()5698 POSTING_READ(CDCLK_CTL); in skl_dpll0_enable()5793 I915_WRITE(CDCLK_CTL, freq_select | skl_cdclk_decimal(freq)); in skl_set_cdclk()5794 POSTING_READ(CDCLK_CTL); in skl_set_cdclk()6703 uint32_t cdctl = I915_READ(CDCLK_CTL); in skylake_get_display_clock_speed()6749 uint32_t cdctl = I915_READ(CDCLK_CTL); in broxton_get_display_clock_speed()
7394 #define CDCLK_CTL 0x46000 macro