Searched refs:CACHE_LINE_SIZE (Results 1 - 10 of 10) sorted by relevance

/linux-4.1.27/arch/arm/mm/
H A Dcache-xsc3l2.c27 #define CACHE_LINE_SIZE 32 macro
112 if (start & (CACHE_LINE_SIZE - 1)) { xsc3_l2_inv_range()
113 vaddr = l2_map_va(start & ~(CACHE_LINE_SIZE - 1), vaddr); xsc3_l2_inv_range()
116 start = (start | (CACHE_LINE_SIZE - 1)) + 1; xsc3_l2_inv_range()
122 while (start < (end & ~(CACHE_LINE_SIZE - 1))) { xsc3_l2_inv_range()
125 start += CACHE_LINE_SIZE; xsc3_l2_inv_range()
148 start &= ~(CACHE_LINE_SIZE - 1); xsc3_l2_clean_range()
152 start += CACHE_LINE_SIZE; xsc3_l2_clean_range()
191 start &= ~(CACHE_LINE_SIZE - 1); xsc3_l2_flush_range()
196 start += CACHE_LINE_SIZE; xsc3_l2_flush_range()
H A Dcache-feroceon-l2.c137 #define CACHE_LINE_SIZE 32 macro
146 BUG_ON(start & (CACHE_LINE_SIZE - 1)); calc_range_end()
147 BUG_ON(end & (CACHE_LINE_SIZE - 1)); calc_range_end()
176 if (start & (CACHE_LINE_SIZE - 1)) { feroceon_l2_inv_range()
177 l2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); feroceon_l2_inv_range()
178 start = (start | (CACHE_LINE_SIZE - 1)) + 1; feroceon_l2_inv_range()
184 if (start < end && end & (CACHE_LINE_SIZE - 1)) { feroceon_l2_inv_range()
185 l2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); feroceon_l2_inv_range()
186 end &= ~(CACHE_LINE_SIZE - 1); feroceon_l2_inv_range()
194 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); feroceon_l2_inv_range()
208 start &= ~(CACHE_LINE_SIZE - 1); feroceon_l2_clean_range()
209 end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1); feroceon_l2_clean_range()
212 l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE); feroceon_l2_clean_range()
222 start &= ~(CACHE_LINE_SIZE - 1); feroceon_l2_flush_range()
223 end = (end + CACHE_LINE_SIZE - 1) & ~(CACHE_LINE_SIZE - 1); feroceon_l2_flush_range()
227 l2_clean_pa_range(start, range_end - CACHE_LINE_SIZE); feroceon_l2_flush_range()
228 l2_inv_pa_range(start, range_end - CACHE_LINE_SIZE); feroceon_l2_flush_range()
H A Dcache-tauros2.c62 #define CACHE_LINE_SIZE 32 macro
69 if (start & (CACHE_LINE_SIZE - 1)) { tauros2_inv_range()
70 tauros2_clean_inv_pa(start & ~(CACHE_LINE_SIZE - 1)); tauros2_inv_range()
71 start = (start | (CACHE_LINE_SIZE - 1)) + 1; tauros2_inv_range()
77 if (end & (CACHE_LINE_SIZE - 1)) { tauros2_inv_range()
78 tauros2_clean_inv_pa(end & ~(CACHE_LINE_SIZE - 1)); tauros2_inv_range()
79 end &= ~(CACHE_LINE_SIZE - 1); tauros2_inv_range()
87 start += CACHE_LINE_SIZE; tauros2_inv_range()
95 start &= ~(CACHE_LINE_SIZE - 1); tauros2_clean_range()
98 start += CACHE_LINE_SIZE; tauros2_clean_range()
106 start &= ~(CACHE_LINE_SIZE - 1); tauros2_flush_range()
109 start += CACHE_LINE_SIZE; tauros2_flush_range()
H A Dcache-l2x0.c48 #define CACHE_LINE_SIZE 32 macro
193 start += CACHE_LINE_SIZE; __l2c210_op_pa_range()
201 if (start & (CACHE_LINE_SIZE - 1)) { l2c210_inv_range()
202 start &= ~(CACHE_LINE_SIZE - 1); l2c210_inv_range()
204 start += CACHE_LINE_SIZE; l2c210_inv_range()
207 if (end & (CACHE_LINE_SIZE - 1)) { l2c210_inv_range()
208 end &= ~(CACHE_LINE_SIZE - 1); l2c210_inv_range()
220 start &= ~(CACHE_LINE_SIZE - 1); l2c210_clean_range()
229 start &= ~(CACHE_LINE_SIZE - 1); l2c210_flush_range()
303 start += CACHE_LINE_SIZE; l2c220_op_pa_range()
321 if ((start | end) & (CACHE_LINE_SIZE - 1)) { l2c220_inv_range()
322 if (start & (CACHE_LINE_SIZE - 1)) { l2c220_inv_range()
323 start &= ~(CACHE_LINE_SIZE - 1); l2c220_inv_range()
325 start += CACHE_LINE_SIZE; l2c220_inv_range()
328 if (end & (CACHE_LINE_SIZE - 1)) { l2c220_inv_range()
329 end &= ~(CACHE_LINE_SIZE - 1); l2c220_inv_range()
347 start &= ~(CACHE_LINE_SIZE - 1); l2c220_clean_range()
366 start &= ~(CACHE_LINE_SIZE - 1); l2c220_flush_range()
471 if ((start | end) & (CACHE_LINE_SIZE - 1)) { l2c310_inv_range_erratum()
478 if (start & (CACHE_LINE_SIZE - 1)) { l2c310_inv_range_erratum()
479 start &= ~(CACHE_LINE_SIZE - 1); l2c310_inv_range_erratum()
482 start += CACHE_LINE_SIZE; l2c310_inv_range_erratum()
485 if (end & (CACHE_LINE_SIZE - 1)) { l2c310_inv_range_erratum()
486 end &= ~(CACHE_LINE_SIZE - 1); l2c310_inv_range_erratum()
513 start += CACHE_LINE_SIZE; l2c310_flush_range_erratum()
959 CACHE_LINE_SIZE); l2x0_cache_size_of_parse()
960 line_size = CACHE_LINE_SIZE; l2x0_cache_size_of_parse()
964 if (line_size != CACHE_LINE_SIZE) l2x0_cache_size_of_parse()
968 CACHE_LINE_SIZE); l2x0_cache_size_of_parse()
1287 start &= ~(CACHE_LINE_SIZE - 1); aurora_pa_range()
1288 end = ALIGN(end, CACHE_LINE_SIZE); aurora_pa_range()
1298 writel_relaxed(range_end - CACHE_LINE_SIZE, base + offset); aurora_pa_range()
H A Dcache-v6.S21 #define CACHE_LINE_SIZE 32 define
135 bic r0, r0, #CACHE_LINE_SIZE - 1
138 add r0, r0, #CACHE_LINE_SIZE
/linux-4.1.27/arch/m68k/coldfire/
H A Dcache.c40 : "i" (CACHE_LINE_SIZE), mcf_cache_push()
/linux-4.1.27/arch/m68k/include/asm/
H A Dm53xxacr.h64 #define CACHE_LINE_SIZE 16 /* 16 byte line size */ macro
H A Dm54xxacr.h64 #define CACHE_LINE_SIZE 0x0010 /* 16 bytes */ macro
/linux-4.1.27/arch/x86/pci/
H A Dolpc.c292 * CACHE_LINE_SIZE, or PM registers. pci_olpc_write()
/linux-4.1.27/drivers/pci/
H A Dpci.c2852 * pci_set_cacheline_size - ensure the CACHE_LINE_SIZE register is programmed

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