Searched refs:CACHELINE_BYTES (Results 1 – 4 of 4) sorted by relevance
68 CACHELINE_BYTES = L1_CACHE_BYTES define112 addi r6,r6,CACHELINE_BYTES350 addi r3,r3,CACHELINE_BYTES354 addi r3,r3,CACHELINE_BYTES
14 #define CACHELINE_BYTES 64 macro15 #define CACHELINE_DWORDS (CACHELINE_BYTES / sizeof(uint32_t))
220 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in intel_emit_post_sync_nonzero_flush()257 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen6_render_ring_flush()330 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen7_render_ring_flush()415 u32 scratch_addr = req->ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen8_render_ring_flush()1466 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in pc_render_add_request()1488 scratch_addr += 2 * CACHELINE_BYTES; /* write to separate cachelines */ in pc_render_add_request()1490 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()1492 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()1494 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()1496 scratch_addr += 2 * CACHELINE_BYTES; in pc_render_add_request()[all …]
1250 scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES; in gen8_init_indirectctx_bb()1699 u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; in gen8_emit_flush_render()