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Searched refs:BY_AL7230_REG_LEN (Results 1 - 1 of 1) sorted by relevance

/linux-4.4.14/drivers/staging/vt6655/
H A D	rf.c	47 #define BY_AL7230_REG_LEN 23 /* 24bit / macro 174 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Channel1 // Need modify for 11a / 175 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Channel1 // Need modify for 11a / 176 0x841FF200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11a: 451FE2 / 177 0x3FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11a: 5FDFA3 / 178 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / 11b/g // Need modify for 11a / 180 0x802B5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11a: 8D1B55 / 181 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 182 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11a: 860207 / 183 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 184 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 185 0xE0000A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11a: E0600A / 186 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) / 188 0x000A3C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11a: 00143C / 189 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 190 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 191 0x1ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW / Need modify for 11a: 12BACF / 195 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Channel184 // Need modify for 11b/g / 196 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Channel184 // Need modify for 11b/g / 197 0x451FE200+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11b/g / 198 0x5FDFA300+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11b/g / 199 0x67F78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / 11a // Need modify for 11b/g / 200 0x853F5500+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11b/g, RoberYu:20050113 / 201 0x56AF3600+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 202 0xCE020700+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11b/g / 203 0x6EBC0800+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 204 0x221BB900+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 205 0xE0600A00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11b/g / 206 0x08031B00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / init 0x080B1B00 => 0x080F1B00 for 3 wire control TxGain(D10) / 207 0x00147C00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / Need modify for 11b/g / 208 0xFFFFFD00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 209 0x00000E00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, 210 0x12BACF00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW / Need modify for 11b/g / 214 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 1, Tf = 2412MHz / 215 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 2, Tf = 2417MHz / 216 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 3, Tf = 2422MHz / 217 0x00379000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 4, Tf = 2427MHz / 218 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 5, Tf = 2432MHz / 219 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 6, Tf = 2437MHz / 220 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 7, Tf = 2442MHz / 221 0x0037A000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 8, Tf = 2447MHz //RobertYu: 20050218, update for APNode 0.49 / 222 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 9, Tf = 2452MHz //RobertYu: 20050218, update for APNode 0.49 / 223 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 10, Tf = 2457MHz //RobertYu: 20050218, update for APNode 0.49 / 224 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 11, Tf = 2462MHz //RobertYu: 20050218, update for APNode 0.49 / 225 0x0037B000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 12, Tf = 2467MHz //RobertYu: 20050218, update for APNode 0.49 / 226 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 13, Tf = 2472MHz //RobertYu: 20050218, update for APNode 0.49 / 227 0x0037C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 14, Tf = 2484MHz / 230 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 183, Tf = 4915MHz (15) / 231 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 184, Tf = 4920MHz (16) / 232 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 185, Tf = 4925MHz (17) / 233 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 187, Tf = 4935MHz (18) / 234 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 188, Tf = 4940MHz (19) / 235 0x0FF52000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 189, Tf = 4945MHz (20) / 236 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 192, Tf = 4960MHz (21) / 237 0x0FF53000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 196, Tf = 4980MHz (22) / 242 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 7, Tf = 5035MHz (23) / 243 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 8, Tf = 5040MHz (24) / 244 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 9, Tf = 5045MHz (25) / 245 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 11, Tf = 5055MHz (26) / 246 0x0FF54000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 12, Tf = 5060MHz (27) / 247 0x0FF55000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 16, Tf = 5080MHz (28) / 248 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 34, Tf = 5170MHz (29) / 249 0x0FF56000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 36, Tf = 5180MHz (30) / 250 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 38, Tf = 5190MHz (31) //RobertYu: 20050218, update for APNode 0.49 / 251 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 40, Tf = 5200MHz (32) / 252 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 42, Tf = 5210MHz (33) / 253 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 44, Tf = 5220MHz (34) / 254 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 46, Tf = 5230MHz (35) / 255 0x0FF57000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 48, Tf = 5240MHz (36) / 256 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 52, Tf = 5260MHz (37) / 257 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 56, Tf = 5280MHz (38) / 258 0x0FF58000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 60, Tf = 5300MHz (39) / 259 0x0FF59000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 64, Tf = 5320MHz (40) / 261 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 100, Tf = 5500MHz (41) / 262 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 104, Tf = 5520MHz (42) / 263 0x0FF5C000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 108, Tf = 5540MHz (43) / 264 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 112, Tf = 5560MHz (44) / 265 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 116, Tf = 5580MHz (45) / 266 0x0FF5D000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 120, Tf = 5600MHz (46) / 267 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 124, Tf = 5620MHz (47) / 268 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 128, Tf = 5640MHz (48) / 269 0x0FF5E000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 132, Tf = 5660MHz (49) / 270 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 136, Tf = 5680MHz (50) / 271 0x0FF5F000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 140, Tf = 5700MHz (51) / 272 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 149, Tf = 5745MHz (52) / 273 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 153, Tf = 5765MHz (53) / 274 0x0FF60000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 157, Tf = 5785MHz (54) / 275 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 161, Tf = 5805MHz (55) / 276 0x0FF61000+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW / channel = 165, Tf = 5825MHz (56) / 280 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 1, Tf = 2412MHz / 281 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 2, Tf = 2417MHz / 282 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 3, Tf = 2422MHz / 283 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 4, Tf = 2427MHz / 284 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 5, Tf = 2432MHz / 285 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 6, Tf = 2437MHz / 286 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 7, Tf = 2442MHz / 287 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 8, Tf = 2447MHz / 288 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 9, Tf = 2452MHz / 289 0x1B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 10, Tf = 2457MHz / 290 0x03333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 11, Tf = 2462MHz / 291 0x0B333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 12, Tf = 2467MHz / 292 0x13333100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 13, Tf = 2472MHz / 293 0x06666100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 14, Tf = 2484MHz / 296 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 183, Tf = 4915MHz (15) / 297 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 184, Tf = 4920MHz (16) / 298 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 185, Tf = 4925MHz (17) / 299 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 187, Tf = 4935MHz (18) / 300 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 188, Tf = 4940MHz (19) / 301 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 189, Tf = 4945MHz (20) / 302 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 192, Tf = 4960MHz (21) / 303 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 196, Tf = 4980MHz (22) / 307 0x1D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 7, Tf = 5035MHz (23) / 308 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 8, Tf = 5040MHz (24) / 309 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 9, Tf = 5045MHz (25) / 310 0x08000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 11, Tf = 5055MHz (26) / 311 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 12, Tf = 5060MHz (27) / 312 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 16, Tf = 5080MHz (28) / 313 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 34, Tf = 5170MHz (29) / 314 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 36, Tf = 5180MHz (30) / 315 0x10000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 38, Tf = 5190MHz (31) / 316 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 40, Tf = 5200MHz (32) / 317 0x1AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 42, Tf = 5210MHz (33) / 318 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 44, Tf = 5220MHz (34) / 319 0x05555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 46, Tf = 5230MHz (35) / 320 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 48, Tf = 5240MHz (36) / 321 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 52, Tf = 5260MHz (37) / 322 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 56, Tf = 5280MHz (38) / 323 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 60, Tf = 5300MHz (39) / 324 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 64, Tf = 5320MHz (40) / 325 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 100, Tf = 5500MHz (41) / 326 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 104, Tf = 5520MHz (42) / 327 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 108, Tf = 5540MHz (43) / 328 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 112, Tf = 5560MHz (44) / 329 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 116, Tf = 5580MHz (45) / 330 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 120, Tf = 5600MHz (46) / 331 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 124, Tf = 5620MHz (47) / 332 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 128, Tf = 5640MHz (48) / 333 0x0AAAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 132, Tf = 5660MHz (49) / 334 0x15555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 136, Tf = 5680MHz (50) / 335 0x00000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 140, Tf = 5700MHz (51) / 336 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 149, Tf = 5745MHz (52) / 337 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 153, Tf = 5765MHz (53) / 338 0x0D555100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 157, Tf = 5785MHz (54) / 339 0x18000100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 161, Tf = 5805MHz (55) / 340 0x02AAA100+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW / channel = 165, Tf = 5825MHz (56) / 344 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 1, Tf = 2412MHz / 345 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 2, Tf = 2417MHz / 346 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 3, Tf = 2422MHz / 347 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 4, Tf = 2427MHz / 348 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 5, Tf = 2432MHz / 349 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 6, Tf = 2437MHz / 350 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 7, Tf = 2442MHz / 351 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 8, Tf = 2447MHz / 352 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 9, Tf = 2452MHz / 353 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 10, Tf = 2457MHz / 354 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 11, Tf = 2462MHz / 355 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 12, Tf = 2467MHz / 356 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 13, Tf = 2472MHz / 357 0x7FD78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 14, Tf = 2484MHz / 360 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 183, Tf = 4915MHz (15) / 361 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 184, Tf = 4920MHz (16) / 362 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 185, Tf = 4925MHz (17) / 363 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 187, Tf = 4935MHz (18) / 364 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 188, Tf = 4940MHz (19) / 365 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 189, Tf = 4945MHz (20) / 366 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 192, Tf = 4960MHz (21) / 367 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 196, Tf = 4980MHz (22) / 371 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 7, Tf = 5035MHz (23) / 372 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 8, Tf = 5040MHz (24) / 373 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 9, Tf = 5045MHz (25) / 374 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 11, Tf = 5055MHz (26) / 375 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 12, Tf = 5060MHz (27) / 376 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 16, Tf = 5080MHz (28) / 377 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 34, Tf = 5170MHz (29) / 378 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 36, Tf = 5180MHz (30) / 379 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 38, Tf = 5190MHz (31) / 380 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 40, Tf = 5200MHz (32) / 381 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 42, Tf = 5210MHz (33) / 382 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 44, Tf = 5220MHz (34) / 383 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 46, Tf = 5230MHz (35) / 384 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 48, Tf = 5240MHz (36) / 385 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 52, Tf = 5260MHz (37) / 386 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 56, Tf = 5280MHz (38) / 387 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 60, Tf = 5300MHz (39) / 388 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 64, Tf = 5320MHz (40) / 389 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 100, Tf = 5500MHz (41) / 390 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 104, Tf = 5520MHz (42) / 391 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 108, Tf = 5540MHz (43) / 392 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 112, Tf = 5560MHz (44) / 393 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 116, Tf = 5580MHz (45) / 394 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 120, Tf = 5600MHz (46) / 395 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 124, Tf = 5620MHz (47) / 396 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 128, Tf = 5640MHz (48) / 397 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 132, Tf = 5660MHz (49) / 398 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 136, Tf = 5680MHz (50) / 399 0x67D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 140, Tf = 5700MHz (51) / 400 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 149, Tf = 5745MHz (52) / 401 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 153, Tf = 5765MHz (53) / 402 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 157, Tf = 5785MHz (54) / 403 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW, / channel = 161, Tf = 5805MHz (55) / 404 0x77D78400+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW / channel = 165, Tf = 5825MHz (56) */ 443 bResult &= IFRFbWriteEmbedded(priv, (0x9ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); s_bAL7230Init() 446 bResult &= IFRFbWriteEmbedded(priv, (0x3ABA8F00+(BY_AL7230_REG_LEN<<3)+IFREGCTL_REGW)); s_bAL7230Init() 880 (BY_AL7230_REG_LEN << 3) \| IFREGCTL_REGW; RFbRawSetPower()

Completed in 201 milliseconds