Searched refs:BIT8 (Results 1 – 11 of 11) sorted by relevance
230 #define IMR_HIGHDOK BIT8249 #define TPPoll_HCCAQ BIT8379 #define RRSR_24M BIT8
56 #define BIT8 0x00000100 macro
109 #define ALGO_TRACE_SW_DETAIL BIT8
26 #define BIT8 0x00000100 macro
26 #define BIT8 0x0100 macro
503 #define RXSTATUS_SHORT_FRAME BIT8504 #define RXSTATUS_CODE_VIOLATION BIT8565 #define MISCSTATUS_DSR BIT8588 #define SICR_DSR_INACTIVE BIT8589 #define SICR_DSR (BIT9|BIT8)1642 usc_OutDmaReg(info, CDIR, BIT8 | BIT0 ); in mgsl_isr_transmit_dma()4836 RegValue |= BIT9 | BIT8; in usc_set_sdlc_mode()4838 RegValue |= ( BIT12 | BIT10 | BIT9 | BIT8); in usc_set_sdlc_mode()5005 case HDLC_ENCODING_NRZI_SPACE: RegValue |= BIT8; break; in usc_set_sdlc_mode()5009 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: RegValue |= BIT9 | BIT8; break; in usc_set_sdlc_mode()[all …]
419 #define IRQ_RXOVER BIT82378 if (gsr & (BIT8 << i)) in slgt_interrupt()4161 val |= BIT8; in async_mode()4201 val |= BIT8; in async_mode()4250 if ((rd_reg32(info, JCR) & BIT8) && info->params.data_rate && in async_mode()4323 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()4396 case HDLC_CRC_32_CCITT: val |= BIT9 + BIT8; break; in sync_mode()5039 if (!(*(src+1) & (BIT9 + BIT8))) { in loopback_test_rx()
67 #define BIT8 0x00000100 macro
392 #define RRSR_24M BIT8
682 #define LPFC_SLI4_INTR8 BIT8
297 #define IRQ_TXFIFO BIT8 // transmit pool ready