| /linux-4.4.14/drivers/video/fbdev/via/ |
| H A D | via_utility.c | 152 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); viafb_set_gamma_table()
162 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7); viafb_set_gamma_table()
207 viafb_write_reg_mask(SR16, VIASR, 0x80, BIT7); viafb_get_gamma_table()
217 viafb_write_reg_mask(CR33, VIACR, 0x80, BIT7); viafb_get_gamma_table()
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| H A D | lcd.c | 390 viafb_write_reg_mask(CRA2, VIACR, 0xC0, BIT7 + BIT6); load_lcd_scaling()
402 viafb_write_reg_mask(CRA2, VIACR, 0x00, BIT7); load_lcd_scaling()
625 viafb_write_reg_mask(CRD3, VIACR, 0xC0, BIT6 + BIT7); integrated_lvds_disable()
634 viafb_write_reg_mask(CR91, VIACR, 0xC0, BIT6 + BIT7); integrated_lvds_disable()
641 viafb_write_reg_mask(CRD2, VIACR, 0x80, BIT7); integrated_lvds_disable()
653 viafb_write_reg_mask(CRD2, VIACR, 0xC0, BIT6 + BIT7); integrated_lvds_disable()
677 viafb_write_reg_mask(CR91, VIACR, 0, BIT6 + BIT7); integrated_lvds_enable()
686 viafb_write_reg_mask(CRD3, VIACR, 0, BIT6 + BIT7); integrated_lvds_enable()
696 viafb_write_reg_mask(CRD2, VIACR, 0, BIT7); integrated_lvds_enable()
708 viafb_write_reg_mask(CRD2, VIACR, 0, BIT6 + BIT7); integrated_lvds_enable()
760 BIT7 + BIT2 + BIT1 + BIT0); set_lcd_output_path()
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| H A D | dvi.c | 69 viafb_write_reg_mask(SR1E, VIASR, 0xC0, BIT6 + BIT7); viafb_tmds_trasmitter_identify()
76 BIT5 + BIT6 + BIT7); viafb_tmds_trasmitter_identify()
467 viafb_write_reg_mask(CR91, VIACR, 0, BIT7); viafb_dvi_enable()
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| H A D | hw.c | 481 viafb_write_reg_mask(CR11, VIACR, BIT7, BIT7); viafb_lock_crt()
486 viafb_write_reg_mask(CR11, VIACR, 0, BIT7); viafb_unlock_crt()
960 viafb_write_reg_mask(CR03, VIACR, 0x80, BIT7); load_fix_bit_crtc_reg()
1684 viafb_write_reg_mask(SR1B, VIASR, 0x00, BIT7 + BIT6); viafb_init_dac()
1691 viafb_write_reg_mask(SR1B, VIASR, 0xC0, BIT7 + BIT6); viafb_init_dac()
2049 viafb_write_reg_mask(CR6A, VIACR, BIT7, BIT7); enable_second_display_channel()
2057 viafb_write_reg_mask(CR6A, VIACR, 0x00, BIT7); disable_second_display_channel()
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| H A D | share.h | 35 #define BIT7 0x80 macro
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| /linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8821ae/ |
| H A D | pwrseq.h | 54 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
115 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
174 PWR_BASEADDR_MAC, PWR_CMD_WRITE, 0x80, BIT7 \
235 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
240 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
304 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
307 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
423 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
521 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
562 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT3 | BIT7, 0 \
595 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, BIT7 \
600 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT7, 0 \
661 PWR_BASEADDR_MAC, PWR_CMD_POLLING, BIT7, 0 \
664 PWR_BASEADDR_MAC, PWR_CMD_WRITE, BIT6|BIT7, 0 \
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| /linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/btcoexist/ |
| H A D | halbt_precomp.h | 55 #define BIT7 0x00000080 macro
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| H A D | halbtc8723b2ant.h | 33 #define BT_INFO_8723B_2ANT_B_FTP BIT7
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| H A D | halbtc8821a2ant.h | 30 #define BT_INFO_8821A_2ANT_B_FTP BIT7
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| H A D | halbtc8192e2ant.h | 30 #define BT_INFO_8192E_2ANT_B_FTP BIT7
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| H A D | halbtc8723b1ant.h | 30 #define BT_INFO_8723B_1ANT_B_FTP BIT7
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| H A D | halbtc8821a1ant.h | 32 #define BT_INFO_8821A_1ANT_B_FTP BIT7
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| H A D | halbtcoutsrc.h | 108 #define ALGO_TRACE_SW BIT7
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| /linux-4.4.14/drivers/staging/rtl8192e/rtl8192e/ |
| H A D | r8192E_hw.h | 231 #define IMR_COMDOK BIT7
248 #define TPPoll_HQ BIT7
378 #define RRSR_18M BIT7
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| /linux-4.4.14/drivers/staging/rtl8192e/ |
| H A D | rtl819x_Qos.h | 25 #define BIT7 0x00000080 macro
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| H A D | rtllib.h | 466 #define FC_QOS_BIT BIT7
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| /linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192de/ |
| H A D | led.c | 59 /* BIT7 of REG_LEDCFG2 should be set to rtl92de_sw_led_on()
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| H A D | reg.h | 391 #define RRSR_18M BIT7
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| /linux-4.4.14/include/uapi/linux/ |
| H A D | synclink.h | 25 #define BIT7 0x0080 macro
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| /linux-4.4.14/drivers/char/pcmcia/ |
| H A D | synclink_cs.c | 298 #define IRQ_RXEOM BIT7 // receive message end
678 #define CMD_RXFIFO BIT7 // release current rx FIFO
924 // BIT7:parity error rx_ready_async()
927 if (status & (BIT7 + BIT6)) { rx_ready_async()
928 if (status & BIT7) rx_ready_async()
939 if (status & BIT7) rx_ready_async()
1235 if (gis & BIT7) { mgslpc_isr()
1483 info->read_status_mask |= BIT7 | BIT6; mgslpc_change_params()
1485 info->ignore_status_mask |= BIT7 | BIT6; mgslpc_change_params()
3189 val |= BIT7 | BIT6; hdlc_mode()
3364 /* power up both channels (set BIT7) */ reset_device()
3601 if (read_reg(info, CHB + VSTR) & BIT7) get_signals()
3680 if (!(status & BIT7) || (status & BIT4)) rx_get_frame()
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| /linux-4.4.14/drivers/scsi/ |
| H A D | dc395x.h | 68 #define BIT7 0x00000080 macro
136 #define DATAOUT BIT7
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| /linux-4.4.14/drivers/tty/ |
| H A D | synclinkmp.c | 415 #define TXINTE BIT7
421 #define UDRN BIT7
434 #define EOM BIT7
2343 /* BIT7 = EOT (end of transfer) isr_rxdmaok()
2600 if (timerstatus0 & (BIT7 | BIT6)) synclinkmp_interrupt()
2604 if (timerstatus1 & (BIT7 | BIT6)) synclinkmp_interrupt()
4575 case HDLC_ENCODING_BIPHASE_MARK: RegValue |= BIT7 + BIT5; break; /* aka FM1 */ hdlc_mode()
4576 case HDLC_ENCODING_BIPHASE_SPACE: RegValue |= BIT7 + BIT6; break; /* aka FM0 */ hdlc_mode()
4577 case HDLC_ENCODING_BIPHASE_LEVEL: RegValue |= BIT7; break; /* aka Manchester */ hdlc_mode()
5158 /* DMA Master Enable, BIT7: 1=enable all channels */ sca_init()
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| H A D | synclink_gt.c | 420 #define IRQ_DSR BIT7
2891 val |= BIT7; set_interface()
2893 val &= ~BIT7; set_interface()
4156 val |= BIT7; async_mode()
4307 val |= BIT7; sync_mode()
4424 val |= BIT7; /* 100, txclk = DPLL Input */ sync_mode()
4447 val = BIT7; break; sync_mode()
4450 val = BIT7 + BIT6; break; sync_mode()
4574 val |= BIT7 + BIT6 + BIT5; /* 1110 */ msc_set_vcr()
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| H A D | synclink.c | 505 #define RXSTATUS_EXITED_HUNT BIT7
545 #define TXSTATUS_PREAMBLE_SENT BIT7
566 #define MISCSTATUS_DCD_LATCHED BIT7
590 #define SICR_DCD_ACTIVE BIT7
592 #define SICR_DCD (BIT7|BIT6)
626 #define TXSTATUS_PREAMBLE_SENT BIT7
2911 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7)); mgsl_break()
2913 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7)); mgsl_break()
5211 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6)); usc_enable_loopback()
5250 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6)); usc_enable_loopback()
7632 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ; usc_loopmode_active()
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| /linux-4.4.14/drivers/misc/altera-stapl/ |
| H A D | altera.c | 486 * BIT7 - FORCED ON altera_execute()
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| /linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8192cu/ |
| H A D | hw.c | 2257 "pwrdown, 0x5c(BIT7)=%02x\n", u1tmp); rtl92cu_gpio_radio_on_off_checking()
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| /linux-4.4.14/drivers/net/wireless/realtek/rtlwifi/rtl8723be/ |
| H A D | hw.c | 1124 /* Configuration Space offset 0x70f BIT7 is used to control L0S */ _rtl8723be_enable_aspm_back_door()
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| /linux-4.4.14/drivers/scsi/lpfc/ |
| H A D | lpfc_hw4.h | 681 #define LPFC_SLI4_INTR7 BIT7
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