Searched refs:BIT11 (Results 1 – 11 of 11) sorted by relevance
78 #define BIT11 0x00000800 macro160 #define EP3_INT BIT11187 #define EP3_EN BIT11228 #define EP0_IN_NAK_INT BIT11241 #define EP0_STATUS_RW_BIT (BIT16|BIT15|BIT11|0xFF)247 #define EP0_IN_NAK_EN BIT11281 #define EPn_IPIDCLR BIT11344 #define EPn_STOP_MODE BIT11
227 #define IMR_RDU BIT11252 #define TPPoll_StopVI BIT11382 #define RRSR_54M BIT11
59 #define BIT11 0x00000800 macro
29 #define BIT11 0x00000800 macro
29 #define BIT11 0x0800 macro
64 #define BIT11 0x00000800 macro
415 #define IRQ_TXUNDER BIT11 /* HDLC */4312 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; in sync_mode()4313 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()4316 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()4317 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()4385 case HDLC_ENCODING_NRZI_MARK: val |= BIT11; break; in sync_mode()4386 case HDLC_ENCODING_NRZI: val |= BIT11 + BIT10; break; in sync_mode()4389 case HDLC_ENCODING_BIPHASE_LEVEL: val |= BIT12 + BIT11; break; in sync_mode()4390 case HDLC_ENCODING_DIFF_BIPHASE_LEVEL: val |= BIT12 + BIT11 + BIT10; break; in sync_mode()
544 #define TCSR_UNDERWAIT BIT11562 #define MISCSTATUS_RI_LATCHED BIT11584 #define SICR_RI_ACTIVE BIT11586 #define SICR_RI (BIT11|BIT10)4966 RegValue |= BIT11; in usc_set_sdlc_mode()5164 case HDLC_PREAMBLE_LENGTH_32BITS: RegValue |= BIT11; break; in usc_set_sdlc_mode()5165 case HDLC_PREAMBLE_LENGTH_64BITS: RegValue |= BIT11 | BIT10; break; in usc_set_sdlc_mode()
395 #define RRSR_54M BIT11
685 #define LPFC_SLI4_INTR11 BIT11
294 #define IRQ_TIMER BIT11 // timer interrupt