Searched refs:BC_Write_Reg (Results 1 - 35 of 35) sorted by relevance

/linux-4.4.14/drivers/isdn/hisax/
H A Djade.c28 cs->BC_Write_Reg(cs, -1, 0x50, 0x19); JadeVersion()
56 cs->BC_Write_Reg(cs, -1, COMM_JADE + 1, value); jade_write_indirect()
58 cs->BC_Write_Reg(cs, -1, COMM_JADE, reg); jade_write_indirect()
89 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (mode == L1_MODE_TRANS ? jadeMODE_TMO : 0x00)); modejade()
90 cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR0, (jadeCCR0_PU | jadeCCR0_ITF)); modejade()
91 cs->BC_Write_Reg(cs, jade, jade_HDLC_CCR1, 0x00); modejade()
98 cs->BC_Write_Reg(cs, jade, jade_HDLC_XCCR, 0x07); modejade()
99 cs->BC_Write_Reg(cs, jade, jade_HDLC_RCCR, 0x07); modejade()
102 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x00); modejade()
103 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x00); modejade()
105 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAX, 0x04); modejade()
106 cs->BC_Write_Reg(cs, jade, jade_HDLC_TSAR, 0x04); modejade()
110 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, jadeMODE_TMO); modejade()
113 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_TMO | jadeMODE_RAC | jadeMODE_XAC)); modejade()
116 cs->BC_Write_Reg(cs, jade, jade_HDLC_MODE, (jadeMODE_RAC | jadeMODE_XAC)); modejade()
120 cs->BC_Write_Reg(cs, jade, jade_HDLC_RCMD, (jadeRCMD_RRES | jadeRCMD_RMC)); modejade()
121 cs->BC_Write_Reg(cs, jade, jade_HDLC_XCMD, jadeXCMD_XRES); modejade()
123 cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0xF8); modejade()
127 cs->BC_Write_Reg(cs, jade, jade_HDLC_IMR, 0x00); modejade()
258 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00); clear_pending_jade_ints()
259 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00); clear_pending_jade_ints()
270 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0xF8); clear_pending_jade_ints()
271 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0xF8); clear_pending_jade_ints()
289 cs->BC_Write_Reg(cs, 0, jade_HDLC_MODE, jadeMODE_TMO); initjade()
290 cs->BC_Write_Reg(cs, 1, jade_HDLC_MODE, jadeMODE_TMO); initjade()
292 cs->BC_Write_Reg(cs, 0, jade_HDLC_CCR0, 0x00); initjade()
293 cs->BC_Write_Reg(cs, 1, jade_HDLC_CCR0, 0x00); initjade()
295 cs->BC_Write_Reg(cs, 0, jade_HDLC_IMR, 0x00); initjade()
296 cs->BC_Write_Reg(cs, 1, jade_HDLC_IMR, 0x00); initjade()
300 cs->BC_Write_Reg(cs, -1, jade_INT, (jadeINT_HDLC1 | jadeINT_HDLC2)); initjade()
H A Dhscx.c51 cs->BC_Write_Reg(cs, hscx, HSCX_XAD1, 0xFF); modehscx()
52 cs->BC_Write_Reg(cs, hscx, HSCX_XAD2, 0xFF); modehscx()
53 cs->BC_Write_Reg(cs, hscx, HSCX_RAH2, 0xFF); modehscx()
54 cs->BC_Write_Reg(cs, hscx, HSCX_XBCH, 0x0); modehscx()
55 cs->BC_Write_Reg(cs, hscx, HSCX_RLCR, 0x0); modehscx()
56 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1, modehscx()
58 cs->BC_Write_Reg(cs, hscx, HSCX_CCR2, 0x30); modehscx()
59 cs->BC_Write_Reg(cs, hscx, HSCX_XCCR, 7); modehscx()
60 cs->BC_Write_Reg(cs, hscx, HSCX_RCCR, 7); modehscx()
67 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, modehscx()
69 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, modehscx()
72 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, bcs->hw.hscx.tsaxr1); modehscx()
73 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, bcs->hw.hscx.tsaxr1); modehscx()
77 cs->BC_Write_Reg(cs, hscx, HSCX_TSAX, 0x1f); modehscx()
78 cs->BC_Write_Reg(cs, hscx, HSCX_TSAR, 0x1f); modehscx()
79 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x84); modehscx()
82 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0xe4); modehscx()
85 cs->BC_Write_Reg(cs, hscx, HSCX_CCR1, modehscx()
87 cs->BC_Write_Reg(cs, hscx, HSCX_MODE, 0x8c); modehscx()
91 cs->BC_Write_Reg(cs, hscx, HSCX_CMDR, 0x41); modehscx()
92 cs->BC_Write_Reg(cs, hscx, HSCX_ISTA, 0x00); modehscx()
239 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0xFF); clear_pending_hscx_ints()
240 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0xFF); clear_pending_hscx_ints()
272 cs->BC_Write_Reg(cs, 0, HSCX_MASK, 0); inithscxisac()
273 cs->BC_Write_Reg(cs, 1, HSCX_MASK, 0); inithscxisac()
H A Dhfcscard.c69 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset On */ reset_hfcs()
74 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); /* Reset Off */ reset_hfcs()
80 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CIRM, cs->hw.hfcD.cirm); reset_hfcs()
81 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CLKDEL, 0x0e); reset_hfcs()
82 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_TEST, HFCD_AUTO_AWAKE); /* S/T Auto awake */ reset_hfcs()
84 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); reset_hfcs()
89 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M1, cs->hw.hfcD.int_m1); reset_hfcs()
90 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_INT_M2, cs->hw.hfcD.int_m2); reset_hfcs()
91 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, HFCD_LOAD_STATE | 2); /* HFC ST 2 */ reset_hfcs()
93 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_STATES, 2); /* HFC ST 2 */ reset_hfcs()
95 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); /* HFC Master */ reset_hfcs()
97 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_SCTRL, cs->hw.hfcD.sctrl); reset_hfcs()
128 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcD.ctmt); hfcs_card_msg()
129 cs->BC_Write_Reg(cs, HFCD_DATA, HFCD_MST_MODE, cs->hw.hfcD.mst_m); hfcs_card_msg()
H A Dipacx.c524 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC bch_empty_fifo()
532 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC bch_empty_fifo()
577 while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++); bch_fill_fifo()
578 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a)); bch_fill_fifo()
620 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC bch_int()
660 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES bch_int()
703 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES bch_int()
738 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off bch_mode()
739 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj. bch_mode()
740 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off bch_mode()
741 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments bch_mode()
744 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode bch_mode()
745 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000 bch_mode()
746 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments bch_mode()
747 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); bch_mode()
750 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0 bch_mode()
751 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled bch_mode()
752 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments bch_mode()
753 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); bch_mode()
873 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff); clear_pending_ints()
874 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff); clear_pending_ints()
900 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK); init_ipacx()
901 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK); init_ipacx()
907 cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41); init_ipacx()
908 cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41); init_ipacx()
H A Dw6692.c215 cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT); W6692B_empty_fifo()
222 cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RACT); W6692B_empty_fifo()
260 cs->BC_Write_Reg(cs, bcs->channel, W_B_CMDR, W_B_CMDR_RACT | W_B_CMDR_XMS | (more ? 0 : W_B_CMDR_XME)); W6692B_fill_fifo()
300 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RRST | W_B_CMDR_RACT); W6692B_interrupt()
326 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_RACK | W_B_CMDR_RRST | W_B_CMDR_RACT); W6692B_interrupt()
343 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_XRST | W_B_CMDR_RACT); W6692B_interrupt()
365 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_XRST | W_B_CMDR_RACT); W6692B_interrupt()
738 cs->BC_Write_Reg(cs, bchan, W_B_MODE, 0); W6692Bmode()
741 cs->BC_Write_Reg(cs, bchan, W_B_MODE, W_B_MODE_MMS); W6692Bmode()
744 cs->BC_Write_Reg(cs, bchan, W_B_MODE, W_B_MODE_ITF); W6692Bmode()
745 cs->BC_Write_Reg(cs, bchan, W_B_ADM1, 0xff); W6692Bmode()
746 cs->BC_Write_Reg(cs, bchan, W_B_ADM2, 0xff); W6692Bmode()
750 cs->BC_Write_Reg(cs, bchan, W_B_CMDR, W_B_CMDR_RRST | W6692Bmode()
752 cs->BC_Write_Reg(cs, bchan, W_B_EXIM, 0x00); W6692Bmode()
924 cs->BC_Write_Reg(cs, 0, W_B_EXIM, 0x00); initW6692()
925 cs->BC_Write_Reg(cs, 1, W_B_EXIM, 0x00); initW6692()
1072 cs->BC_Write_Reg = &WriteW6692B; setup_w6692()
H A Disar.c61 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_H, creg); sendmsg()
62 cs->BC_Write_Reg(cs, 0, ISAR_CTRL_L, len); sendmsg()
63 cs->BC_Write_Reg(cs, 0, ISAR_WADR, 0); sendmsg()
65 cs->BC_Write_Reg(cs, 1, ISAR_MBOX, msg[0]); sendmsg()
67 cs->BC_Write_Reg(cs, 2, ISAR_MBOX, msg[i]); sendmsg()
83 cs->BC_Write_Reg(cs, 1, ISAR_HIS, his); sendmsg()
94 cs->BC_Write_Reg(cs, 1, ISAR_RADR, 0); rcv_mbox()
114 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); rcv_mbox()
165 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); ISARVersion()
224 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); isar_load_firmware()
236 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); isar_load_firmware()
350 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, ISAR_IRQSTA); isar_load_firmware()
430 cs->BC_Write_Reg(cs, 0, ISAR_IRQBIT, 0); isar_load_firmware()
499 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
508 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
518 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
525 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
538 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
566 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
602 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
610 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
617 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
664 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_rcv_frame()
1187 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_int_main()
1191 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_int_main()
1207 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_int_main()
1227 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_int_main()
1237 cs->BC_Write_Reg(cs, 1, ISAR_IIA, 0); isar_int_main()
H A Dhfc_2bs0.c94 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip); hfc_clear_fifo()
252 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip); hfc_fill_fifo()
296 cs->BC_Write_Reg(cs, HFC_DATA_NODEB, cip, bcs->tx_skb->data[idx++]); hfc_fill_fifo()
338 cs->BC_Write_Reg(cs, HFC_STATUS, cip, cip); main_irq_hfc()
422 cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt); mode_hfc()
446 cs->BC_Write_Reg(cs, HFC_STATUS, cs->hw.hfc.ctmt, cs->hw.hfc.ctmt); mode_hfc()
H A Davm_a1p.c254 cs->BC_Write_Reg = &WriteHSCX; setup_avm_a1_pcmcia()
H A Disurf.c295 cs->BC_Write_Reg = &WriteISAR; setup_isurf()
H A Dix1_micro.c304 cs->BC_Write_Reg = &WriteHSCX; setup_ix1micro()
H A Dmic.c223 cs->BC_Write_Reg = &WriteHSCX; setup_mic()
H A Dnj_s.c245 cs->BC_Write_Reg = &dummywr; njs_cs_init_rest()
H A Dnj_u.c209 cs->BC_Write_Reg = &dummywr; nju_cs_init_rest()
H A Ds0box.c248 cs->BC_Write_Reg = &WriteHSCX; setup_s0box()
H A Dsaphir.c285 cs->BC_Write_Reg = &WriteHSCX; setup_saphir()
H A Dsportster.c255 cs->BC_Write_Reg = &WriteHSCX; setup_sportster()
H A Dteleint.c330 cs->BC_Write_Reg = &WriteHFC; setup_TeleInt()
H A Dtelespci.c336 cs->BC_Write_Reg = &WriteHSCX; setup_telespci()
H A Davm_a1.c294 cs->BC_Write_Reg = &WriteHSCX; setup_avm_a1()
H A Dbkm_a4t.c311 cs->BC_Write_Reg = &WriteJADE; a4t_cs_init()
H A Dbkm_a8.c424 cs->BC_Write_Reg = &WriteHSCX; setup_sct_quadro()
H A Dniccy.c368 cs->BC_Write_Reg = &WriteHSCX; setup_niccy()
H A Dteles0.c352 cs->BC_Write_Reg = &WriteHSCX; setup_teles0()
H A Ddiva.c944 cs->BC_Write_Reg = &WriteHSCX; setup_diva_common()
962 cs->BC_Write_Reg = &MemWriteHSCX; setup_diva_common()
973 cs->BC_Write_Reg = &MemWriteHSCX_IPACX; setup_diva_common()
H A Dasuscom.c385 cs->BC_Write_Reg = &WriteHSCX; setup_asuscom()
H A Denternow_pci.c375 cs->BC_Write_Reg = &dummywr; en_cs_init_rest()
H A Dteles3.c486 cs->BC_Write_Reg = &WriteHSCX; setup_teles3()
H A Davm_pci.c741 cs->BC_Write_Reg = &WriteHDLC_s; avm_setup_rest()
748 cs->BC_Write_Reg = &WriteHDLCPnP; avm_setup_rest()
H A Dhfc_2bds0.c137 cs->BC_Write_Reg(cs, HFCD_DATA, cip, 0); SelFiFo()
1075 cs->BC_Write_Reg = &WriteReg; set_cs_func()
H A Dsedlbauer.c743 cs->BC_Write_Reg = &WriteHSCX; setup_sedlbauer()
829 cs->BC_Write_Reg = &WriteISAR; setup_sedlbauer()
H A Dgazel.c662 cs->BC_Write_Reg = &WriteHSCX; setup_gazel()
H A Dhisax.h933 void (*BC_Write_Reg) (struct IsdnCardState *, int, u_char, u_char); member in struct:IsdnCardState
H A Delsa.c1175 cs->BC_Write_Reg = &WriteHSCX; setup_elsa_common()
H A Dhfc_sx.c1507 cs->BC_Write_Reg = NULL; setup_hfcsx()
H A Dhfc_pci.c1746 cs->BC_Write_Reg = NULL; setup_hfcpci()

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