/linux-4.4.14/include/sound/ |
H A D | tlv320dac33-plat.h | 20 int keep_bclk; /* Keep the BCLK running in FIFO modes */
|
H A D | soc-dai.h | 56 * BCLK: 57 * - "normal" polarity means signal is available at rising edge of BCLK 58 * - "inverted" polarity means signal is available at falling edge of BCLK 72 #define SND_SOC_DAIFMT_NB_IF (2 << 8) /* normal BCLK + inv FRM */ 73 #define SND_SOC_DAIFMT_IB_NF (3 << 8) /* invert BCLK + nor FRM */ 74 #define SND_SOC_DAIFMT_IB_IF (4 << 8) /* invert BCLK + FRM */
|
/linux-4.4.14/sound/soc/codecs/ |
H A D | wm9713.h | 37 /* Voice DAI BCLK divider */
|
H A D | wm8940.h | 87 /* BCLK clock dividers */
|
H A D | wm8974.h | 68 /* BCLK clock dividers */
|
H A D | wm8510.h | 78 /* BCLK clock dividers */
|
H A D | wm8753.h | 101 /* BCLK clock dividers */
|
H A D | wm9081.c | 662 * gives us a suitable DAC configuration, plus BCLK. configure_clock() 669 /* Make sure we can generate CLK_SYS and BCLK configure_clock() 1020 /* If TDM is set up then that fixes our BCLK. */ wm9081_hw_params() 1026 /* Otherwise work out a BCLK from the sample size */ wm9081_hw_params() 1050 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm9081->bclk); wm9081_hw_params() 1103 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", wm9081_hw_params() 1107 /* LRCLK is a simple fraction of BCLK */ wm9081_hw_params()
|
H A D | max98925.c | 357 /* BCLK/LRCLK ratio calculation */ max98925_set_clock() 470 /* use MCLK for Left channel, right channel always BCLK */ max98925_dai_set_sysclk() 476 /* configure dai clock source to BCLK instead of MCLK */ max98925_dai_set_sysclk()
|
H A D | es8328.h | 291 /* BCLK clock dividers */
|
H A D | pcm512x.c | 576 dev_info(dev, "No SCLK, using BCLK: %ld\n", pcm512x_dai_startup_slave() 583 /* Switch PLL input to BCLK */ pcm512x_dai_startup_slave() 872 dev_err(dev, "Failed to find suitable BCLK: %d\n", ret); pcm512x_set_dividers() 876 dev_err(dev, "No BCLK?\n"); pcm512x_set_dividers() 933 dev_err(dev, "Failed to find BCLK divider\n"); pcm512x_set_dividers() 1054 dev_err(dev, "Failed to write BCLK divider: %d\n", ret); pcm512x_set_dividers()
|
H A D | tlv320dac33.c | 109 u8 burst_bclkdiv; /* BCLK divider value in burst mode */ 112 int keep_bclk; /* Keep the BCLK continuously running 982 * BCLK is only running when data is needed by DAC33 dac33_prepare_chip() 996 * BCLK is only running when data is needed by DAC33 dac33_prepare_chip() 1009 * Set the BCLK as continuous dac33_prepare_chip() 1021 * BCLK divide ratio dac33_prepare_chip()
|
H A D | wm8993.c | 1206 /* What BCLK do we need? */ wm8993_hw_params() 1235 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8993->bclk); wm8993_hw_params() 1288 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", wm8993_hw_params() 1292 /* LRCLK is a simple fraction of BCLK */ wm8993_hw_params()
|
H A D | tlv320aic31xx.h | 84 /* Clock setting register 11, BCLK N Divider */
|
H A D | ak4535.c | 308 /* use 32 fs for BCLK to save power */ ak4535_set_dai_fmt()
|
H A D | wm8523.c | 182 "No matching BCLK/fs ratio for word length %d\n", wm8523_hw_params()
|
H A D | wm8983.c | 708 dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8983->bclk); wm8983_hw_params() 735 dev_err(dai->dev, "No matching BCLK divider found\n"); wm8983_hw_params() 739 dev_dbg(dai->dev, "BCLK div = %d\n", i); wm8983_hw_params()
|
H A D | wm8985.c | 740 dev_dbg(dai->dev, "Target BCLK = %uHz\n", wm8985->bclk); wm8985_hw_params() 767 dev_err(dai->dev, "No matching BCLK divider found\n"); wm8985_hw_params() 771 dev_dbg(dai->dev, "BCLK div = %d\n", i); wm8985_hw_params()
|
H A D | wm5100.c | 1421 /* Target BCLK rate */ wm5100_hw_params() 1426 /* Root for BCLK depends on SYS/ASYNCCLK */ wm5100_hw_params() 1457 dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz %s\n", wm5100_hw_params() 1470 "No valid BCLK for %dHz found from %dHz %s\n", wm5100_hw_params() 1476 dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]); wm5100_hw_params()
|
H A D | wm8995.c | 1627 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", wm8995_hw_params() 1657 if (cur_val < 0) /* BCLK table is sorted */ wm8995_hw_params() 1664 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", wm8995_hw_params()
|
H A D | wm8903.c | 1389 /* CLK_SYS/BCLK ratios - multiplied by 10 due to .5s */ 1550 if (cur_val < 0) /* BCLK table is sorted */ wm8903_hw_params() 1560 dev_dbg(codec->dev, "BCLK ratio %d for %dHz - actual BCLK = %dHz\n", wm8903_hw_params()
|
H A D | wm8904.c | 1290 /* What BCLK do we need? */ wm8904_hw_params() 1319 dev_dbg(codec->dev, "Target BCLK is %dHz\n", wm8904->bclk); wm8904_hw_params() 1376 dev_dbg(codec->dev, "Selected BCLK_DIV of %d for %dHz BCLK\n", wm8904_hw_params() 1380 /* LRCLK is a simple fraction of BCLK */ wm8904_hw_params()
|
H A D | ssm2518.c | 660 * the BCLK pin is left unconnected */ ssm2518_set_sysclk()
|
H A D | tas2552.c | 409 /* out of range PLL_CLKIN, fall back to use BCLK */ tas2552_set_dai_sysclk()
|
H A D | wm2200.c | 1715 /* Target BCLK rate */ wm2200_hw_params() 1735 dev_dbg(codec->dev, "Target BCLK is %dHz, using %dHz SYSCLK\n", wm2200_hw_params() 1748 "No valid BCLK for %dHz found from %dHz SYSCLK\n", wm2200_hw_params() 1754 dev_dbg(codec->dev, "Setting %dHz BCLK\n", bclk_rates[bclk]); wm2200_hw_params()
|
H A D | alc5632.c | 747 /* choose MCLK/BCLK/VBCLK */ alc5632_set_dai_pll() 773 /* values inspired from column BCLK=32Fs of Appendix A table */
|
H A D | ab8500-codec.c | 2193 case SND_SOC_DAIFMT_NB_IF: /* normal BCLK + inv FRM */ ab8500_codec_set_dai_fmt() 2199 case SND_SOC_DAIFMT_IB_NF: /* invert BCLK + nor FRM */ ab8500_codec_set_dai_fmt() 2205 case SND_SOC_DAIFMT_IB_IF: /* invert BCLK + FRM */ ab8500_codec_set_dai_fmt()
|
H A D | wm8962.c | 63 int bclk; /* Desired BCLK */ 2478 dev_dbg(codec->dev, "DSPCLK is %dHz, BCLK %d\n", dspclk, wm8962->bclk); wm8962_configure_bclk() 2493 dev_err(codec->dev, "Unsupported BCLK ratio %d\n", wm8962_configure_bclk() 2608 dev_dbg(codec->dev, "hw_params set BCLK %dHz LRCLK %dHz\n", wm8962_hw_params()
|
H A D | wm8996.c | 1558 /* Pick a divisor for BCLK as close as we can get to ideal */ wm8996_update_bclk() 1562 if (cur_val < 0) /* BCLK table is sorted */ wm8996_update_bclk() 1567 dev_dbg(codec->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", wm8996_update_bclk() 1775 dev_err(codec->dev, "Unsupported BCLK rate: %d\n", bclk_rate); wm8996_hw_params()
|
H A D | es8328.c | 517 /* Master serial port mode, with BCLK generated automatically */ es8328_set_dai_fmt()
|
H A D | rt5631.h | 397 /* CLOCK RELATIVE OF BCLK AND LCRK */
|
H A D | tlv320aic32x4.c | 446 /* BCLK N divider */ aic32x4_hw_params()
|
H A D | wm8978.c | 656 * BCLK polarity mask = 0x100, LRC clock polarity mask = 0x80, wm8978_set_dai_fmt()
|
H A D | wm8994.c | 2867 dev_dbg(dai->dev, "AIF%dCLK is %dHz, target BCLK %dHz\n", wm8994_hw_params() 2903 if (cur_val < 0) /* BCLK table is sorted */ wm8994_hw_params() 2908 dev_dbg(dai->dev, "Using BCLK_DIV %d for actual BCLK %dHz\n", wm8994_hw_params() 2914 dev_err(dai->dev, "Unable to generate LRCLK from %dHz BCLK\n", wm8994_hw_params()
|
H A D | alc5623.c | 595 /* values inspired from column BCLK=32Fs of Appendix A table */
|
H A D | tlv320aic31xx.c | 924 /* set clock on MCLK, BCLK, or GPIO1 as PLL input */ aic31xx_set_dai_sysclk()
|
H A D | arizona.c | 1587 arizona_aif_dbg(dai, "BCLK %dHz LRCLK %dHz\n", arizona_hw_params()
|
H A D | da7213.c | 1189 /* By default only 32 BCLK per WCLK is supported */ da7213_set_dai_fmt()
|
H A D | da9055.c | 1207 /* By default only 32 BCLK per WCLK is supported */ da9055_set_dai_fmt()
|
H A D | rt5631.c | 1364 dev_err(codec->dev, "Fail to get BCLK rate\n"); rt5631_hifi_pcm_params()
|
H A D | wm8753.c | 959 * Set's PCM dai fmt and BCLK.
|
H A D | tlv320aic3x.c | 1218 /* set clock on MCLK or GPIO2 or BCLK */ aic3x_set_dai_sysclk()
|
H A D | wm8995.h | 1816 * R771 (0x303) - AIF1 BCLK 1966 * R787 (0x313) - AIF2 BCLK
|
H A D | wm8996.h | 1780 * R769 (0x301) - AIF1 BCLK 2124 * R801 (0x321) - AIF2 BCLK
|
/linux-4.4.14/sound/soc/atmel/ |
H A D | atmel_ssc_dai.h | 42 #define ATMEL_SSC_CMR_DIV 0 /* MCK divider for BCLK */ 43 #define ATMEL_SSC_TCMR_PERIOD 1 /* BCLK divider for transmit FS */ 44 #define ATMEL_SSC_RCMR_PERIOD 2 /* BCLK divider for receive FS */
|
H A D | atmel_ssc_dai.c | 504 * I2S format, SSC provides BCLK and LRC clocks. atmel_ssc_hw_params() 507 * from the MCK divider, and the BCLK signal atmel_ssc_hw_params() 556 /* I2S format, CODEC supplies BCLK and LRC clocks. */ atmel_ssc_hw_params() 592 /* I2S format, CODEC supplies BCLK, SSC supplies LRCLK. */ atmel_ssc_hw_params() 641 * DSP/PCM Mode A format, SSC provides BCLK and LRC clocks. atmel_ssc_hw_params() 644 * MCK divider, and the BCLK signal is output atmel_ssc_hw_params() 681 * DSP/PCM Mode A format, CODEC supplies BCLK and LRC clocks. atmel_ssc_hw_params() 683 * Data is transferred on first BCLK after LRC pulse rising atmel_ssc_hw_params()
|
/linux-4.4.14/sound/soc/samsung/ |
H A D | snow.c | 48 /* Select I2S Bus clock to set RCLK and BCLK */ snow_late_probe()
|
H A D | h1940_uda1380.c | 108 /* set BCLK division for sample rate */ h1940_hw_params()
|
H A D | rx1950_uda1380.c | 196 /* set BCLK division for sample rate */ rx1950_hw_params()
|
H A D | i2s.c | 71 * Specifically requested RCLK,BCLK by MACHINE Driver. 311 /* Non-TDM I2S controllers do not support BCLK > 48 * FS */ set_bfs() 313 dev_err(&i2s->pdev->dev, "Unsupported BCLK divider\n"); set_bfs() 348 dev_err(&i2s->pdev->dev, "Wrong BCLK Divider!\n"); set_bfs() 862 "RCLK_SRC=%luHz PSR=%u, RCLK=%dfs, BCLK=%dfs\n", config_setup()
|
H A D | neo1973_wm8753.c | 85 /* set codec BCLK division for sample rate */ neo1973_hifi_hw_params()
|
/linux-4.4.14/sound/soc/blackfin/ |
H A D | bf5xx-ssm2602.c | 59 /* CODEC is master for BCLK and LRC in this configuration. */
|
/linux-4.4.14/drivers/media/platform/ |
H A D | arv.c | 132 #define DEFAULT_FREQ 50 /* 50 or 75 (MHz) is available as BCLK */ 133 static int freq = DEFAULT_FREQ; /* BCLK: available 50 or 70 (MHz) */ 220 ar_outl(369, PLDI2CFREQ); /* BCLK = 75MHz */ init_iic() 222 ar_outl(244, PLDI2CFREQ); /* BCLK = 50MHz */ init_iic() 224 ar_outl(244, PLDI2CFREQ); /* default: BCLK = 50MHz */ init_iic()
|
/linux-4.4.14/drivers/staging/fbtft/ |
H A D | fb_st7735r.c | 65 BCLK/2, Opamp current small & Medium low */
|
/linux-4.4.14/drivers/pcmcia/ |
H A D | sa11xx_base.h | 43 * by 2; divide again by 3 (number of BCLK's per command assertion);
|
/linux-4.4.14/drivers/mfd/ |
H A D | wm5102-tables.c | 412 { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */ 417 { 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */ 418 { 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */ 439 { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */ 444 { 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */ 445 { 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */ 454 { 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */ 459 { 0x00000585, 0x0040 }, /* R1413 - AIF3 Tx BCLK Rate */ 460 { 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */
|
H A D | wm8997-tables.c | 294 { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */ 299 { 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */ 300 { 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */ 321 { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */ 326 { 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */ 327 { 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */
|
H A D | wm5110-tables.c | 869 { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */ 874 { 0x00000505, 0x0040 }, /* R1285 - AIF1 Tx BCLK Rate */ 875 { 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */ 896 { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */ 901 { 0x00000545, 0x0040 }, /* R1349 - AIF2 Tx BCLK Rate */ 902 { 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */ 919 { 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */ 924 { 0x00000585, 0x0040 }, /* R1413 - AIF3 Tx BCLK Rate */ 925 { 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */
|
H A D | wm8994-regmap.c | 103 { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */ 111 { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */ 328 { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */ 336 { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */ 556 { 0x0303, 0x0040 }, /* R771 - AIF1 BCLK */ 564 { 0x0313, 0x0040 }, /* R787 - AIF2 BCLK */
|
H A D | wm8998-tables.c | 334 { 0x00000500, 0x000C }, /* R1280 - AIF1 BCLK Ctrl */ 339 { 0x00000506, 0x0040 }, /* R1286 - AIF1 Rx BCLK Rate */ 356 { 0x00000540, 0x000C }, /* R1344 - AIF2 BCLK Ctrl */ 361 { 0x00000546, 0x0040 }, /* R1350 - AIF2 Rx BCLK Rate */ 378 { 0x00000580, 0x000C }, /* R1408 - AIF3 BCLK Ctrl */ 383 { 0x00000586, 0x0040 }, /* R1414 - AIF3 Rx BCLK Rate */
|
H A D | asic3.c | 762 /* HCLK 24.576 MHz, BCLK 12.288 MHz: */ asic3_mmc_enable()
|
/linux-4.4.14/drivers/pinctrl/sunxi/ |
H A D | pinctrl-sun8i-a83t.c | 58 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ 59 SUNXI_FUNCTION(0x3, "tdm"), /* BCLK */ 493 SUNXI_FUNCTION(0x2, "i2s1"), /* BCLK */
|
H A D | pinctrl-sun8i-a33.c | 56 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ 57 SUNXI_FUNCTION(0x3, "aif2"), /* BCLK */
|
H A D | pinctrl-sun6i-a31s.c | 205 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ 671 SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
|
H A D | pinctrl-sun7i-a20.c | 120 SUNXI_FUNCTION(0x6, "i2s1")), /* BCLK */ 175 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ 176 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
|
H A D | pinctrl-sun4i-a10.c | 158 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */ 159 SUNXI_FUNCTION(0x3, "ac97")), /* BCLK */
|
H A D | pinctrl-sun6i-a31.c | 233 SUNXI_FUNCTION(0x2, "i2s0"), /* BCLK */ 755 SUNXI_FUNCTION(0x3, "i2s1"), /* BCLK */
|
H A D | pinctrl-sun5i-a10s.c | 167 SUNXI_FUNCTION(0x2, "i2s"), /* BCLK */
|
/linux-4.4.14/sound/soc/davinci/ |
H A D | davinci-mcasp.c | 551 case 1: /* BCLK divider */ __davinci_mcasp_set_clkdiv() 561 * BCLK/LRCLK ratio descries how many bit-clock cycles __davinci_mcasp_set_clkdiv() 573 "%s(): BCLK/LRCLK %d is not divisible by %d tdm slots", __davinci_mcasp_set_clkdiv() 1030 * If mcasp is BCLK master, and a BCLK divider was not provided by davinci_mcasp_hw_params() 1276 * If we rely on implicit BCLK divider setting we should davinci_mcasp_startup()
|
/linux-4.4.14/arch/sh/drivers/pci/ |
H A D | pci-sh4.h | 124 #define SH4_PCICLKR_BCSTP 0x00000001 /* BCLK Clock Stop */
|
/linux-4.4.14/sound/soc/fsl/ |
H A D | wm1133-ev1.c | 122 /* set codec BCLK division for sample rate */ wm1133_ev1_hw_params()
|
H A D | fsl_ssi.c | 638 * freq: Output BCLK frequency = samplerate * 32 (fixed) * channels
|
/linux-4.4.14/sound/soc/intel/boards/ |
H A D | cht_bsw_rt5672.c | 184 * is in slave mode and 100fs I2S format (BCLK = 100 * LRCLK) cannot cht_codec_init()
|
/linux-4.4.14/arch/arm/mach-omap1/ |
H A D | clock.c | 311 /* MCLK and BCLK divisor selection is not linear: calc_ext_dsor() 347 /* External clock (MCLK & BCLK) functions */ omap1_set_ext_clk_rate()
|
H A D | clock_data.c | 867 /* Amstrad Delta wants BCLK high when inactive */ omap1_clk_init()
|
/linux-4.4.14/sound/pci/oxygen/ |
H A D | oxygen_regs.h | 153 #define OXYGEN_I2S_BCLK_MASK 0x0600 /* BCLK/LRCK */
|
/linux-4.4.14/include/linux/mfd/wm8350/ |
H A D | audio.h | 553 /* BCLK clock dividers */
|
/linux-4.4.14/drivers/pinctrl/sh-pfc/ |
H A D | pfc-emev2.c | 776 /* BCLK, PSYNC, VALID, DATA */ 784 /* BCLK, PSYNC, VALID, DATA */
|
/linux-4.4.14/arch/arm/mach-sa1100/include/mach/ |
H A D | SA-1101.h | 94 #define SKCR_BCLKEn 0x0002 /* Enables BCLK */ 215 #define SKDCR_BCLKEn (1<<9) /* BCLK Divider */
|
H A D | SA-1100.h | 1508 * fbclk, Tbclk Frequency, period of the PCMCIA clock (BCLK). 1519 #define MECR_BSIO Fld (5, 0) /* BCLK Select I/O - 1 [Tmem] */ 1524 #define MECR_BSA Fld (5, 5) /* BCLK Select Attribute - 1 */ 1530 #define MECR_BSM Fld (5, 10) /* BCLK Select Memory - 1 [Tmem] */
|
/linux-4.4.14/sound/pci/hda/ |
H A D | hda_intel.c | 857 /* Intel HSW/BDW display HDA controller is in GPU. Both its power and link BCLK 859 * are used to convert CDClk (Core Display Clock) to 24MHz BCLK: 860 * BCLK = CDCLK * M / N
|
/linux-4.4.14/drivers/pinctrl/berlin/ |
H A D | berlin-bg4ct.c | 322 BERLIN_PINCTRL_FUNCTION(0x4, "adac_test"), /* BCLK */
|
/linux-4.4.14/sound/soc/omap/ |
H A D | omap-mcbsp.c | 451 * Normal BCLK + FS. omap_mcbsp_dai_set_dai_fmt()
|
/linux-4.4.14/sound/soc/pxa/ |
H A D | pxa-ssp.c | 612 * because the data starts clocking out one BCLK pxa_ssp_hw_params()
|
/linux-4.4.14/sound/soc/bcm/ |
H A D | bcm2835-i2s.c | 837 /* BCLK ratio - use default */ bcm2835_i2s_probe()
|
/linux-4.4.14/drivers/media/pci/cx23885/ |
H A D | cx23885-cards.c | 1359 /* GPIO-23 IIS BCLK */ cx23885_gpio_setup() 1513 /* GPIO-23 I2S BCLK */ cx23885_gpio_setup()
|
/linux-4.4.14/include/linux/mfd/arizona/ |
H A D | registers.h | 3761 * R1280 (0x500) - AIF1 BCLK Ctrl 3838 * R1285 (0x505) - AIF1 Tx BCLK Rate 3845 * R1286 (0x506) - AIF1 Rx BCLK Rate 4064 * R1344 (0x540) - AIF2 BCLK Ctrl 4141 * R1349 (0x545) - AIF2 Tx BCLK Rate 4148 * R1350 (0x546) - AIF2 Rx BCLK Rate 4324 * R1408 (0x580) - AIF3 BCLK Ctrl 4401 * R1413 (0x585) - AIF3 Tx BCLK Rate 4408 * R1414 (0x586) - AIF3 Rx BCLK Rate
|
/linux-4.4.14/sound/soc/ |
H A D | soc-core.c | 2141 * snd_soc_dai_set_bclk_ratio - configure BCLK to sample rate ratio. 2143 * @ratio: Ratio of BCLK to Sample rate. 2145 * Configures the DAI for a preset BCLK to sample rate ratio.
|
H A D | soc-pcm.c | 868 * capture-only CODEC is acting as an LRCLK and/or BCLK master soc_pcm_hw_params()
|
/linux-4.4.14/tools/power/x86/turbostat/ |
H A D | turbostat.c | 2586 fprintf(stderr, "SLM BCLK: unknown\n"); slm_bclk() 2590 fprintf(stderr, "SLM BCLK[%d] invalid\n", i); slm_bclk() 2595 fprintf(stderr, "SLM BCLK: %.1f Mhz\n", freq); slm_bclk()
|
/linux-4.4.14/drivers/staging/xgifb/ |
H A D | vb_init.c | 1284 /* chk if BCLK>=100MHz */ XGIInitNew()
|
/linux-4.4.14/sound/pci/ca0106/ |
H A D | ca0106.h | 595 #define SPI_BCP_BIT (1<<3) /* invert BCLK polarity */
|
/linux-4.4.14/sound/spi/ |
H A D | at73c213.c | 146 * or (not here) 384 times the I2S output clock (BCLK). snd_at73c213_set_bitrate()
|
/linux-4.4.14/drivers/net/fddi/skfp/h/ |
H A D | supern_2.h | 1053 * AMD chips use BCLK as unit. 1 BCKL == 2 symbols
|
/linux-4.4.14/drivers/net/fddi/skfp/ |
H A D | smt.c | 1394 * units : internal : 2's complement BCLK smt_fill_mac_status()
|
/linux-4.4.14/include/linux/mfd/wm8994/ |
H A D | registers.h | 2662 * R771 (0x303) - AIF1 BCLK 2824 * R787 (0x313) - AIF2 BCLK
|
/linux-4.4.14/arch/blackfin/mach-bf548/include/mach/ |
H A D | defBF54x_base.h | 1697 #define BCLK 0x6 /* Burst clock frequency */ macro
|