Searched refs:BASE (Results 1 - 106 of 106) sorted by relevance

/linux-4.4.14/drivers/staging/comedi/drivers/
H A Dpcl730.c44 * BASE+0 Isolated outputs 0-7 (write) / inputs 0-7 (read)
45 * BASE+1 Isolated outputs 8-15 (write) / inputs 8-15 (read)
46 * BASE+2 TTL outputs 0-7 (write) / inputs 0-7 (read)
47 * BASE+3 TTL outputs 8-15 (write) / inputs 8-15 (read)
49 * The pcm3730 board does not have register BASE+1.
51 * The pcl725 and p8r8dio only have registers BASE+0 and BASE+1:
53 * BASE+0 Isolated outputs 0-7 (write) (read back on p8r8dio)
54 * BASE+1 Isolated inputs 0-7 (read)
58 * BASE+0 Isolated outputs 0-7 (write) (read back)
59 * BASE+1 Isolated outputs 8-15 (write) (read back)
60 * BASE+2 Isolated inputs 0-7 (read)
61 * BASE+3 Isolated inputs 8-15 (read)
65 * BASE+0 Isolated outputs 0-7 (write) or inputs 0-7 (read)
66 * BASE+1 Isolated outputs 8-15 (write) or inputs 8-15 (read)
67 * BASE+2 Isolated outputs 16-23 (write) or inputs 16-23 (read)
68 * BASE+3 Isolated outputs 24-31 (write) or inputs 24-31 (read)
72 * BASE+0 Isolated outputs 0-7 (write) (read back)
73 * BASE+1 Isolated outputs 8-15 (write) (read back)
74 * BASE+2 Isolated inputs 0-7 (read)
75 * BASE+3 Isolated inputs 8-15 (read)
79 * BASE+2 Relay select register (write)
80 * BASE+3 Board reset control register (write)
81 * BASE+4 Interrupt control register (write)
82 * BASE+4 Change detect 7-0 status register (read)
83 * BASE+5 LED control register (write)
84 * BASE+5 Change detect 15-8 status register (read)
88 * BASE+0 Isolated outputs 0-7 (write)
89 * BASE+1 Isolated outputs 8-15 (write)
93 * BASE+0 Isolated outputs 0-7 (write) (read back)
94 * BASE+1 Isolated outputs 8-15 (write) (read back)
95 * BASE+2 Isolated outputs 16-19 (write) (read back)
96 * BASE+4 Isolated inputs 0-7 (read)
97 * BASE+5 Isolated inputs 8-15 (read)
98 * BASE+6 Isolated inputs 16-19 (read)
/linux-4.4.14/drivers/scsi/
H A Dnsp32.h90 #define IRQ_CONTROL 0x00 /* BASE+00, W, W */
91 #define IRQ_STATUS 0x00 /* BASE+00, W, R */
121 #define TRANSFER_CONTROL 0x02 /* BASE+02, W, W */
122 #define TRANSFER_STATUS 0x02 /* BASE+02, W, R */
139 #define INDEX_REG 0x04 /* BASE+04, Byte(R/W), Word(R) */
141 #define TIMER_SET 0x06 /* BASE+06, W, R/W */
145 #define DATA_REG_LOW 0x08 /* BASE+08, LowW, R/W */
146 #define DATA_REG_HI 0x0a /* BASE+0a, Hi-W, R/W */
148 #define FIFO_REST_CNT 0x0c /* BASE+0c, W, R/W */
153 #define SREQ_SMPL_RATE 0x0f /* BASE+0f, B, R/W */
161 #define SCSI_BUS_CONTROL 0x10 /* BASE+10, B, R/W */
171 #define CLR_COUNTER 0x12 /* BASE+12, B, W */
185 #define SCSI_BUS_MONITOR 0x12 /* BASE+12, B, R */
195 #define COMMAND_DATA 0x14 /* BASE+14, B, R/W */
197 #define PARITY_CONTROL 0x16 /* BASE+16, B, W */
200 #define PARITY_STATUS 0x16 /* BASE+16, B, R */
206 #define RESELECT_ID 0x18 /* BASE+18, B, R */
208 #define COMMAND_CONTROL 0x18 /* BASE+18, W, W */
219 #define SET_ARBIT 0x1a /* BASE+1a, B, W */
223 #define ARBIT_STATUS 0x1a /* BASE+1a, B, R */
230 #define SYNC_REG 0x1c /* BASE+1c, B, R/W */
232 #define ACK_WIDTH 0x1d /* BASE+1d, B, R/W */
234 #define SCSI_DATA_WITH_ACK 0x20 /* BASE+20, B, R/W */
235 #define SCSI_OUT_LATCH_TARGET_ID 0x22 /* BASE+22, B, W */
236 #define SCSI_DATA_IN 0x22 /* BASE+22, B, R */
238 #define SCAM_CONTROL 0x24 /* BASE+24, B, W */
239 #define SCAM_STATUS 0x24 /* BASE+24, B, R */
247 #define SCAM_DATA 0x26 /* BASE+26, B, R/W */
257 #define SACK_CNT 0x28 /* BASE+28, DW, R/W */
258 #define SREQ_CNT 0x2c /* BASE+2c, DW, R/W */
260 #define FIFO_DATA_LOW 0x30 /* BASE+30, B/W/DW, R/W */
261 #define FIFO_DATA_HIGH 0x32 /* BASE+32, B/W, R/W */
262 #define BM_START_ADR 0x34 /* BASE+34, DW, R/W */
264 #define BM_CNT 0x38 /* BASE+38, DW, R/W */
268 #define SGT_ADR 0x3c /* BASE+3c, DW, R/W */
271 #define SCSI_EXECUTE_PHASE 0x40 /* BASE+40, W, R */
288 #define SCSI_CSB_IN 0x42 /* BASE+42, B, R */
290 #define SCSI_MSG_OUT 0x44 /* BASE+44, DW, R/W */
294 #define SEL_TIME_OUT 0x48 /* BASE+48, W, R/W */
295 #define SAVED_SACK_CNT 0x4c /* BASE+4c, DW, R */
297 #define HTOSDATADELAY 0x50 /* BASE+50, B, R/W */
298 #define STOHDATADELAY 0x54 /* BASE+54, B, R/W */
299 #define ACKSUMCHECKRD 0x58 /* BASE+58, W, R */
300 #define REQSUMCHECKRD 0x5c /* BASE+5c, W, R */
307 #define CLOCK_DIV 0x00 /* BASE+08, IDX+00, B, R/W */
312 #define TERM_PWR_CONTROL 0x01 /* BASE+08, IDX+01, B, R/W */
316 #define EXT_PORT_DDR 0x02 /* BASE+08, IDX+02, B, R/W */
317 #define EXT_PORT 0x03 /* BASE+08, IDX+03, B, R/W */
321 #define IRQ_SELECT 0x04 /* BASE+08, IDX+04, W, R/W */
334 #define OLD_SCSI_PHASE 0x05 /* BASE+08, IDX+05, B, R */
340 #define FIFO_FULL_SHLD_COUNT 0x06 /* BASE+08, IDX+06, B, R/W */
341 #define FIFO_EMPTY_SHLD_COUNT 0x07 /* BASE+08, IDX+07, B, R/W */
343 #define EXP_ROM_CONTROL 0x08 /* BASE+08, IDX+08, B, R/W */ /* external ROM control */
348 #define EXP_ROM_ADR 0x09 /* BASE+08, IDX+09, W, R/W */
350 #define EXP_ROM_DATA 0x0a /* BASE+08, IDX+0a, B, R/W */
352 #define CHIP_MODE 0x0b /* BASE+08, IDX+0b, B, R */ /* NinjaSCSI-32Bi only */
361 #define MISC_WR 0x0c /* BASE+08, IDX+0c, W, R/W */
373 #define BM_CYCLE 0x0d /* BASE+08, IDX+0d, B, R/W */
384 #define SREQ_EDGH 0x0e /* BASE+08, IDX+0e, B, W */
387 #define UP_CNT 0x0f /* BASE+08, IDX+0f, B, W */
394 #define CFG_CMD_STR 0x10 /* BASE+08, IDX+10, W, R */
395 #define CFG_LATE_CACHE 0x11 /* BASE+08, IDX+11, W, R/W */
396 #define CFG_BASE_ADR_1 0x12 /* BASE+08, IDX+12, W, R */
397 #define CFG_BASE_ADR_2 0x13 /* BASE+08, IDX+13, W, R */
398 #define CFG_INLINE 0x14 /* BASE+08, IDX+14, W, R */
400 #define SERIAL_ROM_CTL 0x15 /* BASE+08, IDX+15, B, R */
405 #define FIFO_HST_POINTER 0x16 /* BASE+08, IDX+16, B, R/W */
406 #define SREQ_DELAY 0x17 /* BASE+08, IDX+17, B, R/W */
407 #define SACK_DELAY 0x18 /* BASE+08, IDX+18, B, R/W */
408 #define SREQ_NOISE_CANCEL 0x19 /* BASE+08, IDX+19, B, R/W */
409 #define SDP_NOISE_CANCEL 0x1a /* BASE+08, IDX+1a, B, R/W */
410 #define DELAY_TEST 0x1b /* BASE+08, IDX+1b, B, R/W */
411 #define SD0_NOISE_CANCEL 0x20 /* BASE+08, IDX+20, B, R/W */
412 #define SD1_NOISE_CANCEL 0x21 /* BASE+08, IDX+21, B, R/W */
413 #define SD2_NOISE_CANCEL 0x22 /* BASE+08, IDX+22, B, R/W */
414 #define SD3_NOISE_CANCEL 0x23 /* BASE+08, IDX+23, B, R/W */
415 #define SD4_NOISE_CANCEL 0x24 /* BASE+08, IDX+24, B, R/W */
416 #define SD5_NOISE_CANCEL 0x25 /* BASE+08, IDX+25, B, R/W */
417 #define SD6_NOISE_CANCEL 0x26 /* BASE+08, IDX+26, B, R/W */
418 #define SD7_NOISE_CANCEL 0x27 /* BASE+08, IDX+27, B, R/W */
H A Dnsp32.c678 * TODO: sample_rate (BASE+0F) is 0 when internal clock = 40MHz. nsp32_selection_autoscsi()
/linux-4.4.14/include/uapi/linux/
H A Dmii.h22 #define MII_CTRL1000 0x09 /* 1000BASE-T control */
23 #define MII_STAT1000 0x0a /* 1000BASE-T status */
61 #define BMSR_100HALF2 0x0200 /* Can do 100BASE-T2 HDX */
62 #define BMSR_100FULL2 0x0400 /* Can do 100BASE-T2 FDX */
73 #define ADVERTISE_1000XFULL 0x0020 /* Try for 1000BASE-X full-duplex */
75 #define ADVERTISE_1000XHALF 0x0040 /* Try for 1000BASE-X half-duplex */
77 #define ADVERTISE_1000XPAUSE 0x0080 /* Try for 1000BASE-X pause */
79 #define ADVERTISE_1000XPSE_ASYM 0x0100 /* Try for 1000BASE-X asym pause */
96 #define LPA_1000XFULL 0x0020 /* Can do 1000BASE-X full-duplex */
98 #define LPA_1000XHALF 0x0040 /* Can do 1000BASE-X half-duplex */
100 #define LPA_1000XPAUSE 0x0080 /* Can do 1000BASE-X pause */
102 #define LPA_1000XPAUSE_ASYM 0x0100 /* Can do 1000BASE-X pause asym*/
130 /* 1000BASE-T Control register */
131 #define ADVERTISE_1000FULL 0x0200 /* Advertise 1000BASE-T full duplex */
132 #define ADVERTISE_1000HALF 0x0100 /* Advertise 1000BASE-T half duplex */
136 /* 1000BASE-T Status register */
139 #define LPA_1000FULL 0x0800 /* Link partner 1000BASE-T full duplex */
140 #define LPA_1000HALF 0x0400 /* Link partner 1000BASE-T half duplex */
H A Dmdio.h92 /* 10PASS-TS/2BASE-TL */
108 #define MDIO_PMA_SPEED_2B 0x0002 /* 2BASE-TL capable */
113 #define MDIO_PCS_SPEED_10P2B 0x0002 /* 10PASS-TS/2BASE-TL capable */
140 #define MDIO_PMA_CTRL2_1000BT 0x000c /* 1000BASE-T type */
141 #define MDIO_PMA_CTRL2_1000BKX 0x000d /* 1000BASE-KX type */
142 #define MDIO_PMA_CTRL2_100BTX 0x000e /* 100BASE-TX type */
143 #define MDIO_PMA_CTRL2_10BT 0x000f /* 10BASE-T type */
193 #define MDIO_PMA_EXTABLE_1000BT 0x0020 /* 1000BASE-T ability */
194 #define MDIO_PMA_EXTABLE_1000BKX 0x0040 /* 1000BASE-KX ability */
195 #define MDIO_PMA_EXTABLE_100BTX 0x0080 /* 100BASE-TX ability */
196 #define MDIO_PMA_EXTABLE_10BT 0x0100 /* 10BASE-T ability */
/linux-4.4.14/arch/arm/mach-gemini/
H A Dtime.c28 #define TIMER_COUNT(BASE) (IO_ADDRESS(BASE) + 0x00)
29 #define TIMER_LOAD(BASE) (IO_ADDRESS(BASE) + 0x04)
30 #define TIMER_MATCH1(BASE) (IO_ADDRESS(BASE) + 0x08)
31 #define TIMER_MATCH2(BASE) (IO_ADDRESS(BASE) + 0x0C)
/linux-4.4.14/include/linux/
H A Dzutil.h53 #define BASE 65521L /* largest prime smaller than 65536 */ macro
55 /* NMAX is the largest n such that 255n(n+1)/2 + (n+1)(BASE-1) <= 2^32-1 */
100 s1 %= BASE; zlib_adler32()
101 s2 %= BASE; zlib_adler32()
H A Dbrcmphy.h158 #define BCM5482_SHD_MODE_1000BX 0x0001 /* Enable 1000BASE-X registers */
183 #define BCM5482_SSD_1000BX_CTL 0x00 /* 1000BASE-X Control */
H A Dlibata.h1345 * BASE : Common to all libata drivers. The user must set
1358 * All sht initializers (BASE, PIO, BMDMA, NCQ) must be instantiated
/linux-4.4.14/drivers/gpio/
H A Dgpio-104-idio-16.c114 const unsigned BASE = idio_16_base; idio_16_probe() local
122 if (!request_region(BASE, EXTENT, NAME)) { idio_16_probe()
124 NAME, BASE, BASE + EXTENT); idio_16_probe()
139 idio16gpio->base = BASE; idio_16_probe()
156 release_region(BASE, EXTENT); idio_16_probe()
/linux-4.4.14/drivers/media/pci/cobalt/
H A Dcobalt-omnitek.c54 #define BASE (cobalt->bar0) macro
55 #define CAPABILITY_HEADER (BASE)
56 #define CAPABILITY_REGISTER (BASE + 0x04)
59 #define INTERRUPT_STATUS (BASE + 0x08)
60 #define PCI(c) (BASE + 0x40 + ((c) * 0x40))
61 #define SIZE(c) (BASE + 0x58 + ((c) * 0x40))
62 #define DESCRIPTOR(c) (BASE + 0x50 + ((c) * 0x40))
63 #define CS_REG(c) (BASE + 0x60 + ((c) * 0x40))
64 #define BYTES_TRANSFERRED(c) (BASE + 0x64 + ((c) * 0x40))
/linux-4.4.14/drivers/media/tuners/
H A Dtuner-xc2028-types.h12 /* BASE firmware should be loaded before any other firmware */
13 #define BASE (1<<0) macro
14 #define BASE_TYPES (BASE|F8MHZ|MTS|FM|INPUT1|INPUT2|INIT1)
16 /* F8MHZ marks BASE firmwares for 8 MHz Bandwidth */
46 /* There's a FM | BASE firmware + FM specific firmware (std=0) */
H A Dxc4000.c572 if (type & BASE) dump_firm_type_and_int_freq()
573 printk(KERN_CONT "BASE "); dump_firm_type_and_int_freq()
661 & (BASE | INIT1 | FM | DTV6 | DTV7 | DTV78 | DTV8 | SCODE)) seek_firmware()
983 if (priv->cur_fw.type & BASE) { check_firmware()
984 dprintk(1, "BASE firmware not changed.\n"); check_firmware()
988 /* Updating BASE - forget about all currently loaded firmware */ check_firmware()
996 /* BASE firmwares are all std0 */ check_firmware()
998 rc = load_firmware(fe, BASE, &std0); check_firmware()
1007 rc = load_firmware(fe, BASE | INIT1, &std0); check_firmware()
1009 rc = load_firmware(fe, BASE | INIT1, &std0); check_firmware()
1021 if (priv->cur_fw.type == (BASE | new_fw.type) && check_firmware()
1087 * By setting BASE in cur_fw.type only after successfully loading all check_firmware()
1089 * 1. Identify that BASE firmware with type=0 has been loaded; check_firmware()
1090 * 2. Tell whether BASE firmware was just changed the next time through. check_firmware()
1092 priv->cur_fw.type |= BASE; check_firmware()
1545 & (BASE | FM | DTV6 | DTV7 | DTV78 | DTV8)) == BASE) { xc4000_get_frequency()
1578 if (priv->cur_fw.type & BASE) xc4000_get_status()
1605 (priv->cur_fw.type & BASE) != 0) { xc4000_sleep()
1721 id = ((priv->cur_fw.type & BASE) != 0 ? xc4000_attach()
H A Dtuner-xc2028.c181 if (type & BASE) dump_firm_type_and_int_freq()
182 printk("BASE "); dump_firm_type_and_int_freq()
453 if (type & BASE) seek_firmware()
760 (((BASE | new_fw.type) & BASE_TYPES) == check_firmware()
762 tuner_dbg("BASE firmware not changed.\n"); check_firmware()
766 /* Updating BASE - forget about all currently loaded firmware */ check_firmware()
774 /* BASE firmwares are all std0 */ check_firmware()
776 rc = load_firmware(fe, BASE | new_fw.type, &std0); check_firmware()
786 rc = load_firmware(fe, BASE | INIT1 | new_fw.type, &std0); check_firmware()
788 rc = load_firmware(fe, (BASE | INIT1 | new_fw.type) & ~F8MHZ, check_firmware()
801 if (priv->cur_fw.type == (BASE | new_fw.type) && check_firmware()
876 * By setting BASE in cur_fw.type only after successfully loading all check_firmware()
878 * 1. Identify that BASE firmware with type=0 has been loaded; check_firmware()
879 * 2. Tell whether BASE firmware was just changed the next time through. check_firmware()
881 priv->cur_fw.type |= BASE; check_firmware()
/linux-4.4.14/drivers/net/ethernet/dec/tulip/
H A Dde4x5.h224 /* Timings here are for 10BASE-T/AUI only*/
482 #define MII_SR_T4C 0x8000 /* 100BASE-T4 capable */
483 #define MII_SR_TXFD 0x4000 /* 100BASE-TX Full Duplex capable */
484 #define MII_SR_TXHD 0x2000 /* 100BASE-TX Half Duplex capable */
485 #define MII_SR_TFD 0x1000 /* 10BASE-T Full Duplex capable */
486 #define MII_SR_THD 0x0800 /* 10BASE-T Half Duplex capable */
549 #define SROM_10BT 0x0000 /* 10BASE-T half duplex */
550 #define SROM_10BTN 0x0100 /* 10BASE-T with Nway */
551 #define SROM_10BTF 0x0204 /* 10BASE-T full duplex */
552 #define SROM_10BTNLP 0x0400 /* 10BASE-T without Link Pass test */
553 #define SROM_10B2 0x0001 /* 10BASE-2 (BNC) */
554 #define SROM_10B5 0x0002 /* 10BASE-5 (AUI) */
555 #define SROM_100BTH 0x0003 /* 100BASE-T half duplex */
556 #define SROM_100BTF 0x0205 /* 100BASE-T full duplex */
557 #define SROM_100BT4 0x0006 /* 100BASE-T4 */
558 #define SROM_100BFX 0x0007 /* 100BASE-FX half duplex (Fiber) */
559 #define SROM_M10BT 0x0009 /* MII 10BASE-T half duplex */
560 #define SROM_M10BTF 0x020a /* MII 10BASE-T full duplex */
561 #define SROM_M100BT 0x000d /* MII 100BASE-T half duplex */
562 #define SROM_M100BTF 0x020e /* MII 100BASE-T full duplex */
563 #define SROM_M100BT4 0x000f /* MII 100BASE-T4 */
564 #define SROM_M100BF 0x0010 /* MII 100BASE-FX half duplex */
565 #define SROM_M100BFF 0x0211 /* MII 100BASE-FX full duplex */
573 #define SROM_10BASET 0x0000 /* 10BASE-T half duplex */
574 #define SROM_10BASE2 0x0001 /* 10BASE-2 (BNC) */
575 #define SROM_10BASE5 0x0002 /* 10BASE-5 (AUI) */
576 #define SROM_100BASET 0x0003 /* 100BASE-T half duplex */
577 #define SROM_10BASETF 0x0004 /* 10BASE-T full duplex */
578 #define SROM_100BASETF 0x0005 /* 100BASE-T full duplex */
579 #define SROM_100BASET4 0x0006 /* 100BASE-T4 */
580 #define SROM_100BASEF 0x0007 /* 100BASE-FX half duplex */
581 #define SROM_100BASEFF 0x0008 /* 100BASE-FX full duplex */
644 #define SISR_TRA 0x00000200 /* 10BASE-T Receive Port Activity */
/linux-4.4.14/drivers/net/ethernet/atheros/atlx/
H A Datlx.h354 #define MII_LPA_100BASE4 0x0200 /* 100BASE-T4 */
375 /* 1000BASE-T Control Register */
393 /* 1000BASE-T Status Register */
424 #define MII_ATLX_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover
425 * 100BASE-TX/10BASE-T: MDI
431 * 10BASE-T distance
432 * (Lower 10BASE-T RX
434 * 0=Normal 10BASE-T RX
438 * 100BASE-TX
440 * 100BASE-TX
/linux-4.4.14/arch/sparc/kernel/
H A Dsun4v_tlb_miss.S9 /* Load ITLB fault information into VADDR and CTX, using BASE. */
10 #define LOAD_ITLB_INFO(BASE, VADDR, CTX) \
11 ldx [BASE + HV_FAULT_I_ADDR_OFFSET], VADDR; \
12 ldx [BASE + HV_FAULT_I_CTX_OFFSET], CTX;
14 /* Load DTLB fault information into VADDR and CTX, using BASE. */
15 #define LOAD_DTLB_INFO(BASE, VADDR, CTX) \
16 ldx [BASE + HV_FAULT_D_ADDR_OFFSET], VADDR; \
17 ldx [BASE + HV_FAULT_D_CTX_OFFSET], CTX;
H A Dleon_pci_grpci2.c727 priv->irq = ofdev->archdata.irqs[0]; /* BASE IRQ */ grpci2_of_probe()
/linux-4.4.14/fs/xfs/libxfs/
H A Dxfs_da_btree.h143 #define XFS_DA_LOGOFF(BASE, ADDR) ((char *)(ADDR) - (char *)(BASE))
144 #define XFS_DA_LOGRANGE(BASE, ADDR, SIZE) \
145 (uint)(XFS_DA_LOGOFF(BASE, ADDR)), \
146 (uint)(XFS_DA_LOGOFF(BASE, ADDR)+(SIZE)-1)
/linux-4.4.14/arch/sparc/net/
H A Dbpf_jit_comp.c209 #define emit_loadptr(BASE, STRUCT, FIELD, DEST) \
212 *prog++ = LDPTRI | RS1(BASE) | S13(_off) | RD(DEST); \
215 #define emit_load32(BASE, STRUCT, FIELD, DEST) \
218 *prog++ = LD32I | RS1(BASE) | S13(_off) | RD(DEST); \
221 #define emit_load16(BASE, STRUCT, FIELD, DEST) \
224 *prog++ = LD16I | RS1(BASE) | S13(_off) | RD(DEST); \
227 #define __emit_load8(BASE, STRUCT, FIELD, DEST) \
229 *prog++ = LD8I | RS1(BASE) | S13(_off) | RD(DEST); \
232 #define emit_load8(BASE, STRUCT, FIELD, DEST) \
234 __emit_load8(BASE, STRUCT, FIELD, DEST); \
274 #define emit_jmpl(BASE, IMM_OFF, LREG) \
275 *prog++ = (JMPL | IMMED | RS1(BASE) | S13(IMM_OFF) | RD(LREG))
/linux-4.4.14/lib/mpi/
H A Dmpi-pow.c34 * RES = BASE ^ EXP mod MOD
125 } else { /* Make BASE, EXP and MOD not overlap with RES. */ mpi_powm()
127 /* RES and BASE are identical. Allocate temp. space for BASE. */ mpi_powm()
/linux-4.4.14/arch/blackfin/include/asm/
H A Dirq_handler.h24 /* BASE LEVEL interrupt handler routines */
/linux-4.4.14/drivers/net/ethernet/atheros/atl1e/
H A Datl1e_hw.h395 #define REG_RXF0_BASE_ADDR_HI 0x1540 /* share with DESC BASE ADDR HI */
646 /* 1000BASE-T Control Register */
662 #define MII_AT001_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
663 * 100BASE-TX/10BASE-T:
670 /* 1=Enable Extended 10BASE-T distance
671 * (Lower 10BASE-T RX Threshold)
672 * 0=Normal 10BASE-T RX Threshold */
674 /* 1=5-Bit interface in 100BASE-TX
675 * 0=MII interface in 100BASE-TX */
/linux-4.4.14/drivers/ps3/
H A Dps3av_cmd.c501 #define BASE PS3AV_CMD_AUDIO_FS_44K macro
505 [PS3AV_CMD_AUDIO_FS_44K-BASE] = { 6272, 6272, 17836, 17836, 8918 },
506 [PS3AV_CMD_AUDIO_FS_48K-BASE] = { 6144, 6144, 11648, 11648, 5824 },
507 [PS3AV_CMD_AUDIO_FS_88K-BASE] = { 12544, 12544, 35672, 35672, 17836 },
508 [PS3AV_CMD_AUDIO_FS_96K-BASE] = { 12288, 12288, 23296, 23296, 11648 },
509 [PS3AV_CMD_AUDIO_FS_176K-BASE] = { 25088, 25088, 71344, 71344, 35672 },
510 [PS3AV_CMD_AUDIO_FS_192K-BASE] = { 24576, 24576, 46592, 46592, 23296 }
552 ns_val = ps3av_ns_table[PS3AV_CMD_AUDIO_FS_44K-BASE][d]; ps3av_cnv_ns()
559 #undef BASE macro
H A Dps3-lpm.c60 /* BASE SIGNAL GROUP NUMBER macros */
/linux-4.4.14/drivers/net/ethernet/amd/
H A Da2065.h32 * both 10BASE-2 (thin coax) and AUI (DB-15) connectors
62 #define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */
H A Dariadne.h33 * 10BASE-2 (thin coax) and 10BASE-T (UTP) connectors
181 #define CERR 0x0020 /* No Heartbeat (10BASE-T) */
H A Dariadne.c32 * 10BASE-2 (thin coax) and 10BASE-T (UTP) connectors
472 /* Enable Media Interface Port Auto Select (10BASE-2/10BASE-T) */ ariadne_open()
H A D7990.h142 #define LE_C0_CERR 0x2000 /* No Heartbeat (10BASE-T) */
H A Da2065.c37 * both 10BASE-2 (thin coax) and AUI (DB-15) connectors
/linux-4.4.14/drivers/gpu/drm/nouveau/dispnv04/
H A Dtvmodesnv17.c232 * A: [BASE+0x18]...[BASE+0x0] [BASE+0x58]..[BASE+0x40]
233 * B: [BASE+0x34]...[BASE+0x1c] [BASE+0x74]..[BASE+0x5c]
/linux-4.4.14/drivers/net/ethernet/intel/e1000e/
H A D80003es2lan.h58 /* Tx clock speed for Link Down and 1000BASE-T for the following speeds */
H A De1000.h203 u16 ctrl1000; /* 1000BASE-T control register */
204 u16 stat1000; /* 1000BASE-T status register */
H A Ddefines.h714 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
H A Dnetdev.c1155 "PHY 1000BASE-T Status <%x>\n" e1000_print_hw_hang()
/linux-4.4.14/arch/tile/include/arch/
H A Dtrio.h31 * page of the BASE/LIM range is not otherwise written.
/linux-4.4.14/arch/ia64/include/asm/sn/
H A Dklconfig.h46 * on the local node. (LOCAL NODE BASE + offset value gives pointer to
56 * traversed as the local list, using the REMOTE BASE ADDRESS and not
115 * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
H A Dtioca.h581 #define CA_PCI32_DIRECT_BASE 0xC0000000UL /* BASE not configurable */
/linux-4.4.14/drivers/watchdog/
H A Dibmasr.c48 /* JASPER OFFSET FROM SIO BASE ADDR TO ASR S/W REGISTERS. */
155 /* SELECT AND READ THE HIGH-NIBBLE OF THE GPIO BASE ADDRESS */ asr_get_base_address()
159 /* SELECT AND READ THE LOW-NIBBLE OF THE GPIO BASE ADDRESS */ asr_get_base_address()
H A Dsp5100_tco.c368 /* Low three bits of BASE are reserved */
/linux-4.4.14/arch/mips/cavium-octeon/executive/
H A Dcvmx-helper-sgmii.c70 * appropriate value. 1000BASE-X specifies a 10ms __cvmx_helper_sgmii_hardware_init_one_time()
78 /* 1000BASE-X */ __cvmx_helper_sgmii_hardware_init_one_time()
92 * 1000BASE-X mode, tx_Config_Reg<D15:D0> is PCS*_AN*_ADV_REG. __cvmx_helper_sgmii_hardware_init_one_time()
99 /* 1000BASE-X */ __cvmx_helper_sgmii_hardware_init_one_time()
432 /* 1000BASE-X */ __cvmx_helper_sgmii_link_get()
/linux-4.4.14/drivers/net/ethernet/intel/igb/
H A De1000_defines.h660 /* 1000BASE-T Control Register */
668 /* 1000BASE-T Status Register */
884 /* 1000BASE-T: Auto crossover, 100BASE-TX/10BASE-T: MDI Mode */
888 /* 1=Enable Extended 10BASE-T distance (Lower 10BASE-T Rx Threshold
889 * 0=Normal 10BASE-T Rx Threshold
891 /* 1=5-bit interface in 100BASE-TX, 0=MII interface in 100BASE-TX */
914 * within 1ms in 1000BASE-T
/linux-4.4.14/Documentation/video4linux/
H A Dextract_xc3028.pl163 # Firmware 0, type: BASE FW F8MHZ (0x00000003), id: (0000000000000000), size: 6635
172 # Firmware 1, type: BASE FW F8MHZ MTS (0x00000007), id: (0000000000000000), size: 6635
181 # Firmware 2, type: BASE FW FM (0x00000401), id: (0000000000000000), size: 6525
190 # Firmware 3, type: BASE FW FM INPUT1 (0x00000c01), id: (0000000000000000), size: 6539
199 # Firmware 4, type: BASE FW (0x00000001), id: (0000000000000000), size: 6633
208 # Firmware 5, type: BASE FW MTS (0x00000005), id: (0000000000000000), size: 6617
929 # Firmware 0, type: BASE FW F8MHZ (0x00000003), id: (0000000000000000), size: 8718
938 # Firmware 1, type: BASE FW F8MHZ MTS (0x00000007), id: (0000000000000000), size: 8712
947 # Firmware 2, type: BASE FW FM (0x00000401), id: (0000000000000000), size: 8562
956 # Firmware 3, type: BASE FW FM INPUT1 (0x00000c01), id: (0000000000000000), size: 8576
965 # Firmware 4, type: BASE FW (0x00000001), id: (0000000000000000), size: 8706
974 # Firmware 5, type: BASE FW MTS (0x00000005), id: (0000000000000000), size: 8682
/linux-4.4.14/drivers/net/phy/
H A Dnational.c119 pr_debug("10BASE-T HDX loopback %s\n", ns_10_base_t_hdx_loopack()
H A Dbroadcom.c257 * Select 1000BASE-X register set (primary SerDes) bcm5482_config_init()
/linux-4.4.14/arch/m68k/include/asm/
H A Dm68360_quicc.h32 /* BASE + 0x000: user data memory */
40 /* BASE + 0x000: user data memory */
59 /* BASE + 0xc00: PARAMETER RAM */
93 /* BASE + 0x1000: INTERNAL REGISTERS */
/linux-4.4.14/drivers/net/ethernet/sis/
H A Dsis900.h8 * SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
H A Dsis900.c17 SiS 7014 Single Chip 100BASE-TX/10BASE-T Physical Layer Solution,
136 { "AMD 79C901 10BASE-T PHY", 0x0000, 0x6B70, LAN },
/linux-4.4.14/drivers/staging/unisys/include/
H A Dguestlinuxdebug.h147 /* BASE FUNCTIONS */
/linux-4.4.14/drivers/mtd/maps/
H A Dscx200_docflash.c152 printk(KERN_INFO "DOCCS BASE=0x%08lx, CTRL=0x%08lx\n", (long)docmem.start, (long)ctrl); init_scx200_docflash()
/linux-4.4.14/arch/sparc/lib/
H A Dmemset.S37 * Store 64 bytes at (BASE + OFFSET) using value SOURCE. */
/linux-4.4.14/sound/soc/intel/atom/sst/
H A Dsst_pci.c55 "FW LSP DDR BASE does not match with IFWI\n"); sst_platform_get_resources()
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb3/
H A Dvsc8211.c376 SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T"); t3_vsc8211_phy_prep()
390 phy->desc = "1000BASE-X"; t3_vsc8211_phy_prep()
/linux-4.4.14/arch/mips/include/asm/mips-boards/
H A Dbonito64.h411 #define BONITO_PCIMEMBASECFGBASE(WIN, BASE) (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
/linux-4.4.14/drivers/net/ethernet/renesas/
H A Dsh_eth.c482 case 10: /* 10BASE */ sh_eth_set_rate_r8a777x()
485 case 100:/* 100BASE */ sh_eth_set_rate_r8a777x()
547 case 10: /* 10BASE */ sh_eth_set_rate_sh7724()
550 case 100:/* 100BASE */ sh_eth_set_rate_sh7724()
587 case 10: /* 10BASE */ sh_eth_set_rate_sh7757()
590 case 100:/* 100BASE */ sh_eth_set_rate_sh7757()
653 case 10: /* 10BASE */ sh_eth_set_rate_giga()
656 case 100:/* 100BASE */ sh_eth_set_rate_giga()
659 case 1000: /* 1000BASE */ sh_eth_set_rate_giga()
712 case 10: /* 10BASE */ sh_eth_set_rate_gether()
715 case 100:/* 100BASE */ sh_eth_set_rate_gether()
718 case 1000: /* 1000BASE */ sh_eth_set_rate_gether()
H A Dravb_main.c87 case 100: /* 100BASE */ ravb_set_rate()
90 case 1000: /* 1000BASE */ ravb_set_rate()
908 /* 10BASE is not supported */ ravb_phy_init()
/linux-4.4.14/arch/x86/include/asm/uv/
H A Duv_bau.h26 * BAU_SB_DESCRIPTOR_BASE register, set 1 is located at BASE + 512,
27 * set 2 is at BASE + 2*512, set 3 at BASE + 3*512, and so on.
/linux-4.4.14/drivers/rtc/
H A Drtc-ds3232.c38 #define DS3232_REG_ALARM1 0x07 /* Alarm 1 BASE */
39 #define DS3232_REG_ALARM2 0x0B /* Alarm 2 BASE */
/linux-4.4.14/net/ipv4/
H A Dinetpeer.c160 #define rcu_deref_locked(X, BASE) \
161 rcu_dereference_protected(X, lockdep_is_held(&(BASE)->lock.lock))
/linux-4.4.14/drivers/regulator/
H A Dtps51632-regulator.c130 dev_err(tps->dev, "BASE reg write failed, err %d\n", ret); tps51632_init_dcdc()
/linux-4.4.14/drivers/video/fbdev/
H A Ddnfb.c22 * Note: these are the Memory/IO BASE definitions for a mono card set to the
/linux-4.4.14/drivers/net/ethernet/8390/
H A Dhydra.c13 /* and 10BASE-2 (thin coax) and AUI connectors. */
H A Daxnet_cs.c713 PCMCIA_DEVICE_PROD_ID12("PCMCIA", "100BASE", 0x281f1c5d, 0x7c2add04),
H A Dpcnet_cs.c1550 PCMCIA_DEVICE_PROD_ID12("CouplerlessPCMCIA", "100BASE", 0xee5af0ad, 0x7c2add04),
/linux-4.4.14/drivers/net/ethernet/smsc/
H A Dsmc9194.h99 #define BASE 2 macro
H A Dsmc9194.c886 base_address_register = inw( ioaddr + BASE ); smc_probe()
/linux-4.4.14/arch/x86/math-emu/
H A Dget_address.c204 SS INDEX BASE
/linux-4.4.14/arch/mips/include/asm/sn/
H A Dklconfig.h229 * on the local node. (LOCAL NODE BASE + offset value gives pointer to
239 * traversed as the local list, using the REMOTE BASE ADDRESS and not
298 * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
/linux-4.4.14/arch/mips/kernel/
H A Dbmips_vec.S54 /* set up CPU1 CBR; move BASE to 0xa000_0000 */
H A Dtraps.c485 #define BASE 0x03e00000 macro
526 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); simulate_ll()
566 ((unsigned long)(regs->regs[(opcode & BASE) >> 21]) + offset); simulate_sc()
/linux-4.4.14/drivers/net/ethernet/intel/e1000/
H A De1000_hw.h2679 /* 1000BASE-T Control Register */
2695 /* 1000BASE-T Status Register */
2732 #define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
2733 * 100BASE-TX/10BASE-T:
2740 /* 1=Enable Extended 10BASE-T distance
2741 * (Lower 10BASE-T RX Threshold)
2742 * 0=Normal 10BASE-T RX Threshold */
2744 /* 1=5-Bit interface in 100BASE-TX
2745 * 0=MII interface in 100BASE-TX */
2780 * within 1ms in 1000BASE-T
3014 #define IFE_PESC_100BTX_POWER_DOWN 0x0400 /* Indicates the power state of 100BASE-TX */
3015 #define IFE_PESC_10BTX_POWER_DOWN 0x0200 /* Indicates the power state of 10BASE-T */
3016 #define IFE_PESC_POLARITY_REVERSED 0x0100 /* Indicates 10BASE-T polarity */
/linux-4.4.14/drivers/scsi/qla2xxx/
H A Dqla_nx.h466 * ====================== BASE ADDRESSES ON-CHIP ======================
468 * ====================== BASE ADDRESSES ON-CHIP ======================
/linux-4.4.14/drivers/scsi/qla4xxx/
H A Dql4_nx.h491 * ====================== BASE ADDRESSES ON-CHIP ======================
493 * ====================== BASE ADDRESSES ON-CHIP ======================
/linux-4.4.14/drivers/char/hw_random/
H A Dxgene-rng.c354 dev_dbg(&pdev->dev, "APM X-Gene RNG BASE %p ALARM IRQ %d", xgene_rng_probe()
/linux-4.4.14/sound/oss/
H A Daedsp16.c103 jumpers to be configured anyway, only I/O BASE values have to be
1179 "AEDSP16 BASE I/O port region is already in use.\n"); init_aedsp16_mss()
1220 "AEDSP16 BASE I/O port region is already in use.\n"); init_aedsp16_mpu()
1251 DBG(("Initializing BASE[0x%x] IRQ[%d] DMA[%d] MIRQ[%d]\n", init_aedsp16()
/linux-4.4.14/drivers/hwmon/
H A Dpc87360.c76 #define BASE 0x60 /* Register: Base address */ macro
1160 val = (superio_inb(sioaddr, BASE) << 8) pc87360_find()
1161 | superio_inb(sioaddr, BASE + 1); pc87360_find()
/linux-4.4.14/drivers/parisc/
H A Dlba_pci.c1166 * The SBA BASE/MASK registers control CPU -> IO routing. lba_legacy_resources()
1172 * The LBA BASE/MASK registers control IO -> System routing. lba_legacy_resources()
1176 * the LBA BASE/MASE registers to be the exact inverse of lba_legacy_resources()
1181 * reprogram LBA BASE/MASK registers. Thus preserve the code lba_legacy_resources()
/linux-4.4.14/arch/ia64/sn/kernel/
H A Dio_common.c341 "L_IO=%llx L_MEM=%llx BASE=%llx\n", sn_common_bus_fixup()
/linux-4.4.14/drivers/media/rc/
H A Dnuvoton-cir.c137 pr_info(" * CR CIR BASE ADDR: 0x%x\n", cir_dump_regs()
176 pr_info(" * CR CIR WAKE BASE ADDR: 0x%x\n", cir_wake_dump_regs()
H A Dfintek-cir.c121 pr_info(" * CR CIR BASE ADDR: 0x%x\n", cir_dump_regs()
/linux-4.4.14/drivers/mfd/
H A Dlpc_ich.c794 * ACPI BASE register. lpc_ich_enable_acpi_space()
999 * to it we have to read the PMC BASE from config space and address lpc_ich_init_wdt()
/linux-4.4.14/drivers/usb/usbip/
H A Dusbip_common.c284 pr_debug("BASE: cmd %u seq %u devid %u dir %u ep %u\n", usbip_dump_header()
/linux-4.4.14/drivers/ide/
H A Dsiimage.c530 printk(KERN_INFO DRV_NAME " %s: BASE CLOCK %s\n", init_chipset_siimage()
/linux-4.4.14/arch/x86/include/asm/
H A Dcpufeature.h223 #define X86_FEATURE_FSGSBASE ( 9*32+ 0) /* {RD/WR}{FS/GS}BASE instructions*/
/linux-4.4.14/arch/m68k/fpsp040/
H A Dslogn.S356 lea LOGTBL,%a0 | ...BASE ADDRESS OF 1/F AND LOG(F)
/linux-4.4.14/arch/arm/mach-integrator/
H A Dpci_v3.c263 * each of the BASE/MAP pairs in turn (in ascending register number
/linux-4.4.14/sound/isa/
H A Dsc6000.c615 snd_printd("Initializing BASE[0x%lx] IRQ[%d] DMA[%d] MIRQ[%d]\n", snd_sc6000_probe()
/linux-4.4.14/drivers/net/ethernet/dlink/
H A Ddl2k.c265 /* advertise 1000BASE-T half & full duplex, prefer MASTER */ rio_probe1()
280 /* Auto-Negotiation is mandatory for 1000BASE-T, rio_probe1()
/linux-4.4.14/drivers/net/fddi/skfp/h/
H A Dskfbi.h154 #define PCI_ROMBASE 0xfffe0000L /* Bit 31..17: ROM BASE address (1st) */
155 #define PCI_ROMBASZ 0x0001c000L /* Bit 16..14: Treat as BASE or SIZE */
/linux-4.4.14/drivers/net/ethernet/cavium/liquidio/
H A Docteon_device.c460 "BASE", "NIC", "UNKNOWN"};
/linux-4.4.14/drivers/net/ethernet/atheros/atl1c/
H A Datl1c_hw.h789 /* 1000BASE-T Control Register */
/linux-4.4.14/kernel/
H A Dmodule.c84 * Given BASE and SIZE this macro calculates the number of pages the
87 #define MOD_NUMBER_OF_PAGES(BASE, SIZE) (((SIZE) > 0) ? \
88 (PFN_DOWN((unsigned long)(BASE) + (SIZE) - 1) - \
89 PFN_DOWN((unsigned long)BASE) + 1) \
/linux-4.4.14/drivers/net/ethernet/xilinx/
H A Dxilinx_emaclite.c925 /* Don't advertise 1000BASE-T Full/Half duplex speeds */ xemaclite_open()
/linux-4.4.14/drivers/net/ethernet/altera/
H A Daltera_tse_main.c836 /* Stop Advertising 1000BASE Capability if interface is not GMII init_phy()
/linux-4.4.14/drivers/net/ethernet/marvell/
H A Dsky2.c403 /* Fiber: select 1000BASE-X only mode MAC Specific Ctrl Reg. */ sky2_phy_init()
596 /* increase differential signal amplitude in 10BASE-T */ sky2_phy_init()
601 /* fix for IEEE A/B Symmetry failure in 1000BASE-T */ sky2_phy_init()
/linux-4.4.14/drivers/net/ethernet/intel/ixgbe/
H A Dixgbe_x550.c1753 * between the PHYs to match the link speed of the BASE-T link.
/linux-4.4.14/drivers/ntb/hw/intel/
H A Dntb_hw_intel.c2192 * WITHOUT THE BASE ADDRESS, THE SECONDARY SIDE CANNOT DISABLE the
/linux-4.4.14/drivers/net/ethernet/samsung/sxgbe/
H A Dsxgbe_main.c296 /* Stop Advertising 1000BASE Capability if interface is not GMII */ sxgbe_init_phy()
/linux-4.4.14/drivers/net/ethernet/sun/
H A Dniu.h1430 * per RDC group, thus a total of eight) using the BASE and MASK fields
/linux-4.4.14/drivers/net/ethernet/stmicro/stmmac/
H A Dstmmac_main.c850 /* Stop Advertising 1000BASE Capability if interface is not GMII */ stmmac_init_phy()
/linux-4.4.14/arch/mips/kvm/
H A Demulate.c2301 #define BASE 0x03e00000 macro
/linux-4.4.14/drivers/net/ethernet/natsemi/
H A Dnatsemi.c232 MII_FX_SEL = 0x0001, /* 100BASE-FX (fiber) */
/linux-4.4.14/drivers/net/ethernet/chelsio/cxgb4/
H A Dcxgb4_main.c4566 sprintf(bufp, "BASE-%s", t4_get_port_type_description(pi->port_type)); print_port_info()
/linux-4.4.14/arch/m68k/ifpsp060/src/
H A Dfplsp.S8253 lea LOGTBL(%pc),%a0 # BASE ADDRESS OF 1/F AND LOG(F)
H A Dfpsp.S8359 lea LOGTBL(%pc),%a0 # BASE ADDRESS OF 1/F AND LOG(F)
/linux-4.4.14/drivers/gpu/drm/i915/
H A Dintel_display.c15794 err_printf(m, " BASE: %08x\n", error->cursor[i].base); for_each_pipe()

Completed in 4521 milliseconds