Searched refs:B0_R2_CSR (Results 1 – 4 of 4) sorted by relevance
300 #define B0_R2_CSR 0x0074 /* 32 bit BMU control/status reg (rec q 2)(DV)*/ macro
42 B0_R2_CSR = 0x0064, enumerator
3316 skge_write32(hw, B0_R2_CSR, CSR_IRQ_CL_P); in skge_error_irq()
291 queue->rx_bmu_ctl = (HW_PTR) ADDR(B0_R2_CSR) ; in init_rx()