Searched refs:ARM_CKCTL (Results 1 - 6 of 6) sorted by relevance

/linux-4.4.14/arch/arm/mach-omap1/
H A Dsram.S32 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
33 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
34 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
H A Dpm.c204 #define EN_DSPCK 13 /* ARM_CKCTL */
269 ARM_SAVE(ARM_CKCTL); omap1_pm_suspend()
292 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); omap1_pm_suspend()
360 ARM_RESTORE(ARM_CKCTL); omap1_pm_suspend()
418 ARM_SAVE(ARM_CKCTL); omap_pm_debug_show()
473 ARM_SHOW(ARM_CKCTL), omap_pm_debug_show()
H A Dclock_data.c205 * ARM_CKCTL:ARM_INTHCK_SEL(14) to 1
215 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
820 pr_info("Clocks: ARM_SYSST: 0x%04x DPLL_CTL: 0x%04x ARM_CKCTL: 0x%04x\n", omap1_clk_init()
822 omap_readw(ARM_CKCTL)); omap1_clk_init()
876 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); omap1_clk_init()
878 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); omap1_clk_init() local
H A Dclock.c170 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); omap1_ckctl_recalc()
270 regval = omap_readw(ARM_CKCTL); omap1_clk_set_rate_ckctl_arm()
274 omap_writew(regval, ARM_CKCTL); omap1_clk_set_rate_ckctl_arm()
H A Dclock.h236 /* ARM_CKCTL bit shifts */
/linux-4.4.14/arch/arm/mach-omap1/include/mach/
H A Dhardware.h107 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) macro

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