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Searched refs:ARM_CKCTL (Results 1 – 5 of 5) sorted by relevance

/linux-4.4.14/arch/arm/mach-omap1/
Dsram.S32 mov r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0xff000000
33 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x00ff0000
34 orr r3, r3, #OMAP1_IO_ADDRESS(ARM_CKCTL) & 0x0000ff00
Dpm.c269 ARM_SAVE(ARM_CKCTL); in omap1_pm_suspend()
292 omap_writew(omap_readw(ARM_CKCTL) & ~(1 << EN_DSPCK), ARM_CKCTL); in omap1_pm_suspend()
360 ARM_RESTORE(ARM_CKCTL); in omap1_pm_suspend()
418 ARM_SAVE(ARM_CKCTL); in omap_pm_debug_show()
473 ARM_SHOW(ARM_CKCTL), in omap_pm_debug_show()
Dclock_data.c215 .enable_reg = OMAP1_IO_ADDRESS(ARM_CKCTL),
822 omap_readw(ARM_CKCTL)); in omap1_clk_init()
876 omap_writew(omap_readw(ARM_CKCTL) & 0x2fff, ARM_CKCTL); in omap1_clk_init()
878 omap_writew(omap_readw(ARM_CKCTL) & 0x0fff, ARM_CKCTL); in omap1_clk_init()
Dclock.c170 int dsor = 1 << (3 & (omap_readw(ARM_CKCTL) >> clk->rate_offset)); in omap1_ckctl_recalc()
270 regval = omap_readw(ARM_CKCTL); in omap1_clk_set_rate_ckctl_arm()
274 omap_writew(regval, ARM_CKCTL); in omap1_clk_set_rate_ckctl_arm()
/linux-4.4.14/arch/arm/mach-omap1/include/mach/
Dhardware.h107 #define ARM_CKCTL (CLKGEN_REG_BASE + 0x0) macro