Searched refs:APMU_CCIC1 (Results 1 - 2 of 2) sorted by relevance
| /linux-4.4.14/drivers/clk/mmp/ |
| H A D | clk-mmp2.c | 53 #define APMU_CCIC1 0xf4 macro
437 apmu_base + APMU_CCIC1, 6, 2, 0, &clk_lock); mmp2_clk_init()
441 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, mmp2_clk_init()
446 apmu_base + APMU_CCIC1, 0x1b, &clk_lock); mmp2_clk_init()
450 apmu_base + APMU_CCIC1, 0x24, &clk_lock); mmp2_clk_init()
454 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC1, mmp2_clk_init()
459 apmu_base + APMU_CCIC1, 0x300, &clk_lock); mmp2_clk_init()
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| H A D | clk-of-mmp2.c | 55 #define APMU_CCIC1 0xf4 macro
222 {0, "ccic1_sphy_div", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 10, 5, 0, &ccic1_lock},
239 {MMP2_CLK_CCIC1, "ccic1_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x1b, 0x1b, 0x0, 0, &ccic1_lock},
240 {MMP2_CLK_CCIC1_PHY, "ccic1_phy_clk", "ccic1_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x24, 0x24, 0x0, 0, &ccic1_lock},
241 {MMP2_CLK_CCIC1_SPHY, "ccic1_sphy_clk", "ccic1_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC1, 0x300, 0x300, 0x0, 0, &ccic1_lock},
262 ccic1_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC1; mmp2_axi_periph_clk_init()
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Completed in 417 milliseconds