| /linux-4.4.14/drivers/clk/mmp/ |
| D | clk-of-pxa168.c | 47 #define APMU_CCIC0 0x50 macro
193 …{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0…
194 …_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0…
198 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
209 …{PXA168_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, …
210 …{PXA168_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x…
211 …{PXA168_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300…
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| D | clk-pxa910.c | 43 #define APMU_CCIC0 0x50 macro
305 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); in pxa910_clk_init()
309 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in pxa910_clk_init()
315 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); in pxa910_clk_init()
319 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in pxa910_clk_init()
323 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in pxa910_clk_init()
328 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in pxa910_clk_init()
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| D | clk-of-pxa910.c | 46 #define APMU_CCIC0 0x50 macro
199 …{0, "ccic0_mux", ccic_parent_names, ARRAY_SIZE(ccic_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0…
200 …_parent_names, ARRAY_SIZE(ccic_phy_parent_names), CLK_SET_RATE_PARENT, APMU_CCIC0, 7, 1, 0, &ccic0…
204 {0, "ccic0_sphy_div", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
215 …{PXA910_CLK_CCIC0, "ccic0_clk", "ccic0_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0, …
216 …{PXA910_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_phy_mux", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x…
217 …{PXA910_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300…
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| D | clk-of-mmp2.c | 54 #define APMU_CCIC0 0x50 macro
221 {0, "ccic0_sphy_div", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 10, 5, 0, &ccic0_lock},
235 …{MMP2_CLK_CCIC_ARBITER, "ccic_arbiter", "vctcxo", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1800, 0x1800,…
236 …{MMP2_CLK_CCIC0, "ccic0_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x1b, 0x1b, 0x0, 0…
237 …{MMP2_CLK_CCIC0_PHY, "ccic0_phy_clk", "ccic0_mix_clk", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x24, 0x24…
238 …{MMP2_CLK_CCIC0_SPHY, "ccic0_sphy_clk", "ccic0_sphy_div", CLK_SET_RATE_PARENT, APMU_CCIC0, 0x300, …
255 ccic0_mix_config.reg_info.reg_clk_ctrl = pxa_unit->apmu_base + APMU_CCIC0; in mmp2_axi_periph_clk_init()
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| D | clk-pxa168.c | 45 #define APMU_CCIC0 0x50 macro
334 apmu_base + APMU_CCIC0, 6, 1, 0, &clk_lock); in pxa168_clk_init()
338 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in pxa168_clk_init()
344 apmu_base + APMU_CCIC0, 7, 1, 0, &clk_lock); in pxa168_clk_init()
348 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in pxa168_clk_init()
352 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in pxa168_clk_init()
357 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in pxa168_clk_init()
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| D | clk-mmp2.c | 52 #define APMU_CCIC0 0x50 macro
403 apmu_base + APMU_CCIC0, 0x1800, &clk_lock); in mmp2_clk_init()
409 apmu_base + APMU_CCIC0, 6, 2, 0, &clk_lock); in mmp2_clk_init()
413 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
418 apmu_base + APMU_CCIC0, 0x1b, &clk_lock); in mmp2_clk_init()
422 apmu_base + APMU_CCIC0, 0x24, &clk_lock); in mmp2_clk_init()
426 CLK_SET_RATE_PARENT, apmu_base + APMU_CCIC0, in mmp2_clk_init()
431 apmu_base + APMU_CCIC0, 0x300, &clk_lock); in mmp2_clk_init()
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