Searched refs:APBC_RTC (Results 1 - 9 of 9) sorted by relevance

/linux-4.4.14/arch/arm/mach-mmp/
H A Dclock-pxa910.c25 #define APBC_RTC APBC_REG(0x028) macro
H A Dclock-pxa168.c23 #define APBC_RTC APBC_REG(0x028) macro
H A Dclock-mmp2.c16 #define APBC_RTC APBC_REG(0x000) macro
/linux-4.4.14/drivers/clk/mmp/
H A Dclk-of-pxa168.c25 #define APBC_RTC 0x28 macro
147 {PXA168_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
H A Dclk-of-pxa910.c25 #define APBC_RTC 0x28 macro
145 {PXA910_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x83, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, NULL},
H A Dclk-pxa168.c24 #define APBC_RTC 0x28 macro
183 apbc_base + APBC_RTC, 10, 0, &clk_lock); pxa168_clk_init()
H A Dclk-pxa910.c24 #define APBC_RTC 0x28 macro
188 apbc_base + APBC_RTC, 10, 0, &clk_lock); pxa910_clk_init()
H A Dclk-mmp2.c24 #define APBC_RTC 0x0 macro
230 apbc_base + APBC_RTC, 10, 0, &clk_lock); mmp2_clk_init()
H A Dclk-of-mmp2.c25 #define APBC_RTC 0x0 macro
162 {MMP2_CLK_RTC, "rtc_clk", "clk32", CLK_SET_RATE_PARENT, APBC_RTC, 0x87, 0x83, 0x0, MMP_CLK_GATE_NEED_DELAY, &reset_lock},

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