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Searched refs:ADF_CSR_WR (Results 1 – 10 of 10) sorted by relevance

/linux-4.4.14/drivers/crypto/qat/qat_common/
Dadf_transport_access_macros.h129 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
136 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
138 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
142 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
145 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
149 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
151 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
155 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
158 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
162 ADF_CSR_WR(csr_base_addr, (ADF_RING_BUNDLE_SIZE * bank) + \
Dadf_hw_arbiter.c63 ADF_CSR_WR(csr_addr, ADF_ARB_RINGSRVARBEN_OFFSET + \
67 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
71 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
76 ADF_CSR_WR(csr_addr, ADF_ARB_OFFSET + \
80 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
85 ADF_CSR_WR(csr_addr, (ADF_ARB_OFFSET + \
Dadf_pf2vf_msg.c74 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_vintmsk_offset(0), 0x0); in adf_enable_pf2vf_interrupts()
91 ADF_CSR_WR(pmisc_bar_addr, hw_data->get_vintmsk_offset(0), 0x2); in adf_disable_pf2vf_interrupts()
108 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg); in adf_enable_vf2pf_interrupts()
115 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg); in adf_enable_vf2pf_interrupts()
137 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK3, reg); in adf_disable_vf2pf_interrupts()
144 ADF_CSR_WR(pmisc_addr, ADF_DH895XCC_ERRMSK5, reg); in adf_disable_vf2pf_interrupts()
194 ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, msg); in __adf_iov_putmsg()
213 ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, msg | int_bit); in __adf_iov_putmsg()
228 ADF_CSR_WR(pmisc_bar_addr, pf2vf_offset, val & ~local_in_use_mask); in __adf_iov_putmsg()
273 ADF_CSR_WR(pmisc_addr, hw_data->get_pf2vf_offset(vf_nr), msg); in adf_vf2pf_req_hndl()
Dicp_qat_hal.h103 ADF_CSR_WR(handle->hal_cap_g_ctl_csr_addr_v, csr, val)
113 ADF_CSR_WR(AE_CSR_ADDR(handle, ae, csr), 0, val)
121 ADF_CSR_WR(AE_XFER_ADDR(handle, ae, reg), 0, val)
123 ADF_CSR_WR(handle->hal_sram_addr_v, addr, val)
Dadf_admin.c169 ADF_CSR_WR(mailbox, mb_offset, 1); in adf_put_admin_msg_sync()
264 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGUR_OFFSET, reg_val >> 32); in adf_init_admin_comms()
265 ADF_CSR_WR(csr, ADF_DH895XCC_ADMINMSGLR_OFFSET, reg_val); in adf_init_admin_comms()
Dadf_sriov.c71 ADF_CSR_WR(pmisc_bar_addr, ME2FUNCTION_MAP_A_OFFSET + \
79 ADF_CSR_WR(pmisc_bar_addr, ME2FUNCTION_MAP_B_OFFSET + \
Dadf_accel_devices.h184 #define ADF_CSR_WR(csr_base, csr_offset, val) \ macro
Dqat_hal.c453 ADF_CSR_WR(csr_addr, 0, csr_val); in qat_hal_init_esram()
/linux-4.4.14/drivers/crypto/qat/qat_dh895xcc/
Dadf_dh895xcc_hw_data.c186 ADF_CSR_WR(csr, ADF_DH895XCC_AE_CTX_ENABLES(i), val); in adf_enable_error_correction()
189 ADF_CSR_WR(csr, ADF_DH895XCC_AE_MISC_CONTROL(i), val); in adf_enable_error_correction()
196 ADF_CSR_WR(csr, ADF_DH895XCC_UERRSSMSH(i), val); in adf_enable_error_correction()
199 ADF_CSR_WR(csr, ADF_DH895XCC_CERRSSMSH(i), val); in adf_enable_error_correction()
210 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF0_MASK_OFFSET, in adf_enable_ints()
213 ADF_CSR_WR(addr, ADF_DH895XCC_SMIAPF1_MASK_OFFSET, in adf_enable_ints()
/linux-4.4.14/drivers/crypto/qat/qat_dh895xccvf/
Dadf_isr.c128 ADF_CSR_WR(pmisc_bar_addr, ADF_DH895XCCIOV_PF2VF_OFFSET, msg); in adf_pf2vf_bh_handler()