Searched refs:ADCR (Results 1 - 23 of 23) sorted by relevance

/linux-4.4.14/arch/sh/include/cpu-sh3/cpu/
H A Dadc.h26 #define ADCR 0xa4000092 macro
/linux-4.4.14/sound/soc/codecs/
H A Dlm49453.c243 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPL2_REG, 5, 1, 0),
263 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHPR2_REG, 5, 1, 0),
283 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSL2_REG, 5, 1, 0),
303 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLSR2_REG, 5, 1, 0),
323 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAL2_REG, 5, 1, 0),
343 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACHAR2_REG, 5, 1, 0),
363 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOL2_REG, 5, 1, 0),
383 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_DACLOR2_REG, 5, 1, 0),
395 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX1_REG, 5, 1, 0),
406 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX2_REG, 5, 1, 0),
417 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX3_REG, 5, 1, 0),
427 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX4_REG, 5, 1, 0),
437 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX5_REG, 5, 1, 0),
447 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX6_REG, 5, 1, 0),
457 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX7_REG, 5, 1, 0),
467 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT1_TX8_REG, 5, 1, 0),
477 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX1_REG, 5, 1, 0),
488 SOC_DAPM_SINGLE("ADCR Switch", LM49453_P0_PORT2_TX2_REG, 5, 1, 0),
503 SOC_DAPM_SINGLE_TLV("Sidetone ADCR Volume", LM49453_P0_STN_VOL_ADCR_REG,
522 SOC_SINGLE_TLV("ADCR Volume", LM49453_P0_ADC_LEVELR_REG, 0, 63,
665 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
792 { "HPL Mixer", "ADCR Switch", "ADC Right" },
815 { "HPR Mixer", "ADCR Switch", "ADC Right" },
845 { "LSL Mixer", "ADCR Switch", "ADC Right" },
868 { "LSR Mixer", "ADCR Switch", "ADC Right" },
895 { "HAL Mixer", "ADCR Switch", "ADC Right" },
918 { "HAR Mixer", "ADCR Switch", "ADC Right" },
945 { "LOL Mixer", "ADCR Switch", "ADC Right" },
968 { "LOR Mixer", "ADCR Switch", "ADC Right" },
983 { "Port1_1 Mixer", "ADCR Switch", "ADC Right" },
990 { "Port1_2 Mixer", "ADCR Switch", "ADC Right" },
997 { "Port1_3 Mixer", "ADCR Switch", "ADC Right" },
1004 { "Port1_4 Mixer", "ADCR Switch", "ADC Right" },
1011 { "Port1_5 Mixer", "ADCR Switch", "ADC Right" },
1018 { "Port1_6 Mixer", "ADCR Switch", "ADC Right" },
1025 { "Port1_7 Mixer", "ADCR Switch", "ADC Right" },
1032 { "Port1_8 Mixer", "ADCR Switch", "ADC Right" },
1039 { "Port2_1 Mixer", "ADCR Switch", "ADC Right" },
1046 { "Port2_2 Mixer", "ADCR Switch", "ADC Right" },
1086 { "ADCR Mux", "Aux_R", "AUXR Input" },
1087 { "ADCR Mux", "MIC2", "Mic2 Input" },
1091 { "ADC Right", NULL, "ADCR Mux"},
H A D88pm860x-codec.c590 "ADCR", "ADCL",
599 /* ADCR Mux / Mux3 */
601 "ADCL", "ADCR",
610 /* ADCR EC Mux / Mux6 */
612 "ADCR", "EC",
619 SOC_DAPM_ENUM("ADCR EC Mux", adcr_ec_enum);
743 SND_SOC_DAPM_MUX("ADCR EC Mux", SND_SOC_NOPM, 0, 0, &adcr_ec_mux),
837 {"PCM SDO", NULL, "ADCR EC Mux"},
855 {"ADC Left Mux", "ADCR", "Right ADC"},
858 {"ADC Right Mux", "ADCR", "Right ADC"},
865 {"ADCR EC Mux", "ADCR", "ADC Right Mux"},
866 {"ADCR EC Mux", "EC", "EC Mux"},
870 {"I2S Mic Mux", "ADC", "ADCR EC Mux"},
H A Dwm8961.c67 { 33, 0x0000 }, /* R33 - ADCR signal path */
409 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", WM8961_PWR_MGMT_1, 2, 0),
443 { "DACL Sidetone", "Right", "ADCR" },
446 { "DACR Sidetone", "Right", "ADCR" },
463 { "ADCR", NULL, "Right Input" },
464 { "ADCR", NULL, "CLK_DSP" },
H A Dwm8995.c888 SOC_DAPM_ENUM("ADCR Mux", adc_enum);
949 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0, &adcr_mux),
957 SND_SOC_DAPM_ADC("ADCR", NULL, WM8995_POWER_MANAGEMENT_3, 0, 0),
1056 { "ADCR", NULL, "AIF1CLK" },
1057 { "ADCR", NULL, "DSP1CLK" },
1058 { "ADCR", NULL, "SYSDSPCLK" },
1066 { "ADCR", NULL, "IN1R PGA" },
1070 { "ADCR Mux", "ADC", "ADCR" },
1071 { "ADCR Mux", "DMIC", "DMIC1R" },
1078 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
H A Dwm8961.h450 #define WM8961_ADCR 0x0004 /* ADCR */
451 #define WM8961_ADCR_MASK 0x0004 /* ADCR */
452 #define WM8961_ADCR_SHIFT 2 /* ADCR */
453 #define WM8961_ADCR_WIDTH 1 /* ADCR */
532 * R33 (0x21) - ADCR signal path
H A Dwm8993.c891 SND_SOC_DAPM_ADC("ADCR", NULL, WM8993_POWER_MANAGEMENT_2, 0, 0),
927 { "ADCR", NULL, "CLK_SYS" },
928 { "ADCR", NULL, "CLK_DSP" },
931 { "AIFOUTL Mux", "Right", "ADCR" },
933 { "AIFOUTR Mux", "Right", "ADCR" },
944 { "DACL Sidetone", "Right", "ADCR" },
946 { "DACR Sidetone", "Right", "ADCR" },
H A Dwm8737.c247 SND_SOC_DAPM_DAC("ADCR", NULL, WM8737_POWER_MANAGEMENT, 2, 0),
273 { "ADCR", NULL, "PGAR" },
276 { "AIF", NULL, "ADCR" },
H A Dalc5632.c344 SOC_DAPM_ENUM("ADCR Mux", alc5632_adcr_func_enum);
365 SND_SOC_DAPM_MUX("ADCR Mux", SND_SOC_NOPM, 0, 0,
578 {"ADCR Mux", "Stereo ADC", "Right ADC"},
579 {"ADCR Mux", "Voice ADC", "Right ADC"},
580 {"ADCLR", NULL, "ADCR Mux"},
581 {"VAIFTX", NULL, "ADCR Mux"},
H A Dwm8903.c843 SND_SOC_DAPM_ADC("ADCR", NULL, WM8903_POWER_MANAGEMENT_6, 0, 0),
985 { "Left Capture Mux", "Right", "ADCR" },
988 { "Right Capture Mux", "Right", "ADCR" },
995 { "ADCR", NULL, "Right ADC Input" },
996 { "ADCR", NULL, "CLK_DSP" },
1005 { "DACL Sidetone", "Right", "ADCR" },
1007 { "DACR Sidetone", "Right", "ADCR" },
H A Dwm8904.c950 SND_SOC_DAPM_ADC("ADCR", NULL, WM8904_POWER_MANAGEMENT_6, 0, 0),
1080 { "AIFOUTL Mux", "Right", "ADCR" },
1082 { "AIFOUTR Mux", "Right", "ADCR" },
1090 { "ADCR", NULL, "CLK_DSP" },
1091 { "ADCR", NULL, "Right Capture PGA" },
1128 { "Left Sidetone", "Right", "ADCR" },
1132 { "Right Sidetone", "Right", "ADCR" },
H A Dmax98090.c562 SOC_SINGLE_TLV("ADCR Boost Volume", M98090_REG_RIGHT_ADC_LEVEL,
569 SOC_SINGLE_TLV("ADCR Volume", M98090_REG_RIGHT_ADC_LEVEL,
1153 SND_SOC_DAPM_ADC_E("ADCR", NULL, M98090_REG_INPUT_ENABLE,
1311 {"ADCR", NULL, "Right ADC Mixer"},
1313 {"ADCR", NULL, "SHDN"},
1316 {"DMIC Mux", "ADC", "ADCR"},
1342 {"STENR Mux", "Sidetone Right", "ADCR"},
H A Dwm8962.c2155 SND_SOC_DAPM_ADC("ADCR", "Capture", WM8962_PWR_MGMT_1, 2, 0),
2239 { "ADCR", NULL, "SYSCLK" },
2240 { "ADCR", NULL, "TOCLK" },
2241 { "ADCR", NULL, "MIXINR" },
2242 { "ADCR", NULL, "DMIC_ENA" },
2243 { "ADCR", NULL, "DSP2" },
2246 { "STL", "Right", "ADCR" },
2250 { "STR", "Right", "ADCR" },
H A Dmax98088.c481 SOC_SINGLE("ADCR Volume", M98088_REG_34_LVL_ADC_R, 0, 15, 0),
484 SOC_SINGLE("ADCR Boost Volume", M98088_REG_34_LVL_ADC_R, 4, 3, 0),
715 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98088_REG_4C_PWR_EN_IN, 0, 0),
922 {"ADCR", NULL, "Right ADC Mixer"},
H A Dwm8994.c1355 SOC_DAPM_ENUM("ADCR Mux", adc_enum);
1658 SND_SOC_DAPM_MUX_E("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux,
1664 SND_SOC_DAPM_MUX("ADCR Mux", WM8994_POWER_MANAGEMENT_4, 0, 0, &adcr_mux),
1765 SND_SOC_DAPM_ADC("ADCR", NULL, SND_SOC_NOPM, 0, 0),
1842 { "ADCR", NULL, "AIF1CLK" },
1843 { "ADCR", NULL, "DSP1CLK" },
1844 { "ADCR", NULL, "DSPINTCLK" },
1848 { "ADCR Mux", "ADC", "ADCR" },
1849 { "ADCR Mux", "DMIC", "DMIC1R" },
1884 { "AIF1ADC1R Mixer", "ADC/DMIC Switch", "ADCR Mux" },
1965 { "Right Sidetone", "ADC/DMIC1", "ADCR Mux" },
H A Dmax98095.c484 SOC_SINGLE_TLV("ADCR Volume", M98095_05E_LVL_ADC_R, 0, 15, 1,
489 SOC_SINGLE_TLV("ADCR Boost Volume", M98095_05E_LVL_ADC_R, 4, 3, 0,
700 SND_SOC_DAPM_ADC("ADCR", "HiFi Capture", M98095_090_PWR_EN_IN, 1, 0),
901 {"ADCR", NULL, "Right ADC Mixer"},
H A Dwm8900.c543 SND_SOC_DAPM_ADC("ADCR", "Right HiFi Capture", WM8900_REG_POWER2, 0, 0),
591 {"ADCR", NULL, "Right Input Mixer"},
H A Dwm8996.c965 SND_SOC_DAPM_ADC("ADCR", NULL, WM8996_POWER_MANAGEMENT_3, 0, 0),
1121 { "ADCR", NULL, "IN1R PGA" },
1137 { "IN1R Mux", "ADC", "ADCR" },
1145 { "IN2R Mux", "ADC", "ADCR" },
H A Drt5651.c670 static const char * const rt5651_sto2_adc_r1_src[] = {"DD MIXR", "ADCR"};
1195 {"Stereo2 ADC R1 Mux", "ADCR", "ADC R"},
H A Drt5640.c837 "Mono DAC MIXR", "ADCR"
1386 {"Mono ADC R1 Mux", "ADCR", "ADC R"},
H A Dwm_hubs.c989 { "ADCR", NULL, "MIXINR" },
/linux-4.4.14/sound/pci/emu10k1/
H A Dp17v.h69 #define ADC_ATTEN_ADCR 0x0000000f /*ADC Attenuation ADCR */
/linux-4.4.14/sound/pci/ca0106/
H A Dca0106.h520 #define ADC_ATTEN_ADCR 0x0000000f //ADC Attenuation ADCR

Completed in 754 milliseconds