Searched refs:wsr (Results 1 - 28 of 28) sorted by relevance

/linux-4.1.27/arch/xtensa/kernel/
H A Dhead.S57 wsr a2, excsave1
75 wsr a1, windowstart
76 wsr a0, windowbase
80 wsr a1, ps
95 wsr a2, excsave1
117 wsr a2, vecbase
124 wsr a0, ibreakenable
126 wsr a0, icount
128 wsr a0, icountlevel
132 wsr a0, SREG_DBREAKC + _index
139 wsr a0, ccount # not really necessary, but nice
144 wsr a0, lcount
151 wsr a0, SREG_CCOMPARE + _index
158 wsr a0, intenable
159 wsr a2, intclear
164 wsr a0, cpenable
197 wsr a2, ps # (enable reg-windows; progmode stack)
203 wsr a2, SREG_EXCSAVE + XCHAL_DEBUGLEVEL
294 wsr a3, ccount
300 wsr a6, excsave1
345 wsr a1, windowstart
346 wsr a0, windowbase
350 wsr a1, ps
H A Dmxhead.S42 wsr a1, windowstart
43 wsr a0, windowbase
47 wsr a1, ps
H A Dentry.S214 wsr a3, windowstart # set corresponding WINDOWSTART bit
215 wsr a2, windowbase # and WINDOWSTART
506 wsr a2, scompare1
508 wsr a3, ps /* disable interrupts */
520 wsr a1, depc # use DEPC as temp storage
521 wsr a3, windowstart # restore WINDOWSTART
523 wsr a2, windowbase # switch to user's saved WB
663 wsr a2, epc1
664 wsr a3, sar
670 wsr a2, lbeg
672 wsr a3, lend
673 wsr a2, lcount
679 wsr a2, icountlevel
680 wsr a3, icount
695 1: wsr a0, depc
717 wsr a2, depc # save a2 temporarily
719 wsr a2, epc1
722 wsr a2, exccause
729 wsr a2, ps
794 wsr a0, windowstart
795 wsr a1, windowbase
799 wsr a1, ps
866 wsr a1, depc
869 wsr a2, ps
906 wsr a0, epc1
925 wsr a0, epc1
945 wsr a0, excsave1
1135 wsr a3, windowstart # save shifted windowstart
1146 wsr a3, windowbase
1238 wsr a3, windowstart
1245 wsr a3, sar
1270 wsr a0, windowstart
1271 wsr a1, windowbase
1280 wsr a4, ps
1289 wsr a0, excsave1
1336 wsr a2, windowstart # set corrected windowstart
1354 wsr a3, windowbase
1392 wsr a2, depc # exception address
1408 wsr a3, windowbase
1904 wsr a14, ps
H A Dcoprocessor.S47 wsr a0, excsave1
238 wsr a0, excsave1
276 wsr a0, cpenable
339 wsr a0, sar
H A Dalign.S335 wsr a0, sar
419 wsr a4, lcount
422 1: wsr a7, epc1 # skip emulated instruction
430 wsr a4, icount
447 wsr a0, sar
457 wsr a3, excsave1
466 wsr a0, sar
H A Dvectors.S74 wsr a2, depc # save a2
101 wsr a2, depc # save a2
258 wsr a2, depc # save stack pointer temporarily
261 wsr a0, windowbase
306 wsr a0, excsave1
400 wsr a0, depc # replace the saved a0
409 wsr a0, depc # replace the saved a0
449 wsr a2, depc
527 wsr a2, depc
627 wsr a0, excsave2
629 wsr a0, epc1
631 wsr a0, exccause
685 wsr a0, ps
H A Dtraps.c335 __asm__ __volatile__("wsr %0, excsave1\n" : : "a" (excsave1)); trap_init_excsave()
H A Dsetup.c357 " wsr %2, scompare1\n" probed_compare_swap()
/linux-4.1.27/arch/xtensa/platforms/iss/
H A Dsetup.c58 "wsr a2, icountlevel\n\t" platform_restart()
60 "wsr a2, icount\n\t" platform_restart()
62 "wsr a2, ibreakenable\n\t" platform_restart()
64 "wsr a2, lcount\n\t" platform_restart()
66 "wsr a2, ps\n\t" platform_restart()
/linux-4.1.27/arch/xtensa/include/asm/
H A Dspinlock.h43 " wsr %0, scompare1\n" arch_spin_lock()
60 " wsr %0, scompare1\n" arch_spin_trylock()
107 " wsr %0, scompare1\n" arch_write_lock()
125 " wsr %0, scompare1\n" arch_write_trylock()
156 " wsr %1, scompare1\n" arch_read_lock()
176 " wsr %1, scompare1\n" arch_read_trylock()
194 " wsr %1, scompare1\n" arch_read_unlock()
H A Dcmpxchg.h27 " wsr %2, scompare1\n" __cmpxchg_u32()
42 " wsr a15, ps\n" __cmpxchg_u32()
103 * may not occur between the rsil and wsr instructions. By using
115 " wsr %1, scompare1\n" xchg_u32()
129 " wsr a15, ps\n" xchg_u32()
H A Datomic.h34 * wsr a15, PS
39 * may not occur between the rsil and wsr instructions. By using
70 " wsr %1, scompare1\n" \
88 " wsr %1, scompare1\n" \
113 " wsr a15, ps\n" \
131 " wsr a15, ps\n" \
262 " wsr %1, scompare1\n" atomic_clear_mask()
280 " wsr a15, ps\n" atomic_clear_mask()
297 " wsr %1, scompare1\n" atomic_set_mask()
313 " wsr a15, ps\n" atomic_set_mask()
H A Dbitops.h112 " wsr %1, scompare1\n" set_bit()
130 " wsr %1, scompare1\n" clear_bit()
148 " wsr %1, scompare1\n" change_bit()
167 " wsr %1, scompare1\n" test_and_set_bit()
188 " wsr %1, scompare1\n" test_and_clear_bit()
209 " wsr %1, scompare1\n" test_and_change_bit()
H A Dtimex.h46 #define WSR_CCOUNT(r) asm volatile ("wsr %0, ccount" :: "a" (r))
48 #define WSR_CCOMPARE(x,r) asm volatile ("wsr %0,"__stringify(SREG_CCOMPARE)"+"__stringify(x) :: "a"(r))
H A Dinitialize_mmu.h60 wsr a3, atomctl
121 wsr a6, ITLBCFG
122 wsr a6, DTLBCFG
158 wsr a0, ptevaddr
H A Dirqflags.h44 asm volatile("wsr %0, ps; rsync" arch_local_irq_restore()
H A Dfutex.h28 " wsr %0, scompare1\n" \
125 " wsr %1, scompare1\n" futex_atomic_cmpxchg_inatomic()
H A Dtlbflush.h107 __asm__ __volatile__("wsr %0, itlbcfg\n\t" "isync\n\t" set_itlbcfg_register()
113 __asm__ __volatile__("wsr %0, dtlbcfg; dsync\n\t" set_dtlbcfg_register()
119 __asm__ __volatile__(" wsr %0, ptevaddr; isync\n" set_ptevaddr_register()
H A Dmmu_context.h57 __asm__ __volatile__ (" wsr %0, rasid\n\t" set_rasid_register()
H A Dcoprocessor.h100 __asm__ __volatile__("wsr %0, cpenable; rsync" :: "a" (x)); \
H A Dprocessor.h189 #define WSR(v,sr) __asm__ __volatile__ ("wsr %0,"__stringify(sr) :: "a"(v));
/linux-4.1.27/arch/xtensa/boot/boot-elf/
H A Dbootstrap.S52 wsr a0, windowbase
55 wsr a0, windowstart
58 wsr a0, ps
/linux-4.1.27/arch/xtensa/platforms/xt2000/
H A Dsetup.c69 "wsr a2, icountlevel\n\t" platform_restart()
71 "wsr a2, icount\n\t" platform_restart()
73 "wsr a2, ibreakenable\n\t" platform_restart()
75 "wsr a2, lcount\n\t" platform_restart()
77 "wsr a2, ps\n\t" platform_restart()
/linux-4.1.27/arch/xtensa/variants/dc232b/include/variant/
H A Dtie-asm.h84 wsr \at1, ACCLO // MAC16 accumulator
85 wsr \at2, ACCHI
92 wsr \at1, M0 // MAC16 registers
93 wsr \at2, M1
96 wsr \at1, M2
97 wsr \at2, M3
103 wsr \at1, SCOMPARE1 // conditional store option
/linux-4.1.27/arch/xtensa/variants/dc233c/include/variant/
H A Dtie-asm.h157 wsr \at1, ACCLO // MAC16 option
159 wsr \at1, ACCHI // MAC16 option
169 wsr \at1, M0 // MAC16 option
171 wsr \at1, M1 // MAC16 option
173 wsr \at1, M2 // MAC16 option
175 wsr \at1, M3 // MAC16 option
177 wsr \at1, SCOMPARE1 // conditional store option
/linux-4.1.27/arch/xtensa/platforms/xtfpga/
H A Dsetup.c60 "wsr a2, icountlevel\n\t" platform_restart()
62 "wsr a2, icount\n\t" platform_restart()
64 "wsr a2, ibreakenable\n\t" platform_restart()
66 "wsr a2, lcount\n\t" platform_restart()
68 "wsr a2, ps\n\t" platform_restart()
/linux-4.1.27/arch/xtensa/boot/boot-redboot/
H A Dbootstrap.S54 wsr a4, ps
60 wsr a4, windowstart
64 wsr a4, ps
/linux-4.1.27/drivers/dma/
H A Dimx-dma.c122 u16 wsr; member in struct:imx_dma_2d_config
529 (imxdma->slots_2d[i].wsr != d->w))) imxdma_xfer_desc()
539 imxdma->slots_2d[slot].wsr = d->w; imxdma_xfer_desc()

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