| /linux-4.1.27/drivers/usb/host/ |
| H A D | ehci-orion.c | 29 #define wrl(off, val) writel_relaxed((val), hcd->regs + (off)) macro
72 wrl(USB_CAUSE, 0); orion_usb_phy_v1_setup()
73 wrl(USB_MASK, 0); orion_usb_phy_v1_setup()
78 wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET); orion_usb_phy_v1_setup()
85 wrl(USB_IPG, (rdl(USB_IPG) & ~0x7f00) | 0xc00); orion_usb_phy_v1_setup()
91 wrl(USB_PHY_PWR_CTRL, (rdl(USB_PHY_PWR_CTRL) & ~0xc0)| 0x40); orion_usb_phy_v1_setup()
97 wrl(USB_PHY_TX_CTRL, (rdl(USB_PHY_TX_CTRL) & ~0x78) | 0x202040); orion_usb_phy_v1_setup()
104 wrl(USB_PHY_RX_CTRL, (rdl(USB_PHY_RX_CTRL) & ~0xc2003f0) | 0xc0000010); orion_usb_phy_v1_setup()
110 wrl(USB_PHY_IVREF_CTRL, (rdl(USB_PHY_IVREF_CTRL) & ~0x80003 ) | 0x32); orion_usb_phy_v1_setup()
116 wrl(USB_PHY_TST_GRP_CTRL, rdl(USB_PHY_TST_GRP_CTRL) & ~0x8000); orion_usb_phy_v1_setup()
121 wrl(USB_CMD, rdl(USB_CMD) & ~USB_CMD_RUN); orion_usb_phy_v1_setup()
122 wrl(USB_CMD, rdl(USB_CMD) | USB_CMD_RESET); orion_usb_phy_v1_setup()
130 wrl(USB_MODE, USB_MODE_SDIS | USB_MODE_HOST); orion_usb_phy_v1_setup()
140 wrl(USB_WINDOW_CTRL(i), 0); ehci_orion_conf_mbus_windows()
141 wrl(USB_WINDOW_BASE(i), 0); ehci_orion_conf_mbus_windows()
147 wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) | ehci_orion_conf_mbus_windows()
150 wrl(USB_WINDOW_BASE(i), cs->base); ehci_orion_conf_mbus_windows()
|
| /linux-4.1.27/drivers/net/ethernet/cirrus/ |
| H A D | ep93xx_eth.c | 187 #define wrl(ep, off, val) __raw_writel((val), (ep)->base_addr + (off)) macro
195 wrl(ep, REG_MIICMD, REG_MIICMD_READ | (phy_id << 5) | reg); ep93xx_mdio_read()
218 wrl(ep, REG_MIIDATA, data); ep93xx_mdio_write()
219 wrl(ep, REG_MIICMD, REG_MIICMD_WRITE | (phy_id << 5) | reg); ep93xx_mdio_write()
332 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX); ep93xx_poll()
334 wrl(ep, REG_INTEN, REG_INTEN_TX); ep93xx_poll()
335 wrl(ep, REG_INTSTSP, REG_INTSTS_RX); ep93xx_poll()
383 wrl(ep, REG_TXDENQ, 1); ep93xx_xmit()
454 wrl(ep, REG_INTEN, REG_INTEN_TX); ep93xx_irq()
555 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET); ep93xx_start_hw()
567 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9)); ep93xx_start_hw()
571 wrl(ep, REG_SELFCTL, ((ep->mdc_divisor - 1) << 9) | (1 << 8)); ep93xx_start_hw()
575 wrl(ep, REG_RXDQBADD, addr); ep93xx_start_hw()
576 wrl(ep, REG_RXDCURADD, addr); ep93xx_start_hw()
581 wrl(ep, REG_RXSTSQBADD, addr); ep93xx_start_hw()
582 wrl(ep, REG_RXSTSQCURADD, addr); ep93xx_start_hw()
587 wrl(ep, REG_TXDQBADD, addr); ep93xx_start_hw()
588 wrl(ep, REG_TXDQCURADD, addr); ep93xx_start_hw()
593 wrl(ep, REG_TXSTSQBADD, addr); ep93xx_start_hw()
594 wrl(ep, REG_TXSTSQCURADD, addr); ep93xx_start_hw()
597 wrl(ep, REG_BMCTL, REG_BMCTL_ENABLE_TX | REG_BMCTL_ENABLE_RX); ep93xx_start_hw()
598 wrl(ep, REG_INTEN, REG_INTEN_TX | REG_INTEN_RX); ep93xx_start_hw()
599 wrl(ep, REG_GIINTMSK, 0); ep93xx_start_hw()
612 wrl(ep, REG_RXDENQ, RX_QUEUE_ENTRIES); ep93xx_start_hw()
613 wrl(ep, REG_RXSTSENQ, RX_QUEUE_ENTRIES); ep93xx_start_hw()
621 wrl(ep, REG_AFP, 0); ep93xx_start_hw()
623 wrl(ep, REG_MAXFRMLEN, (MAX_PKT_SIZE << 16) | MAX_PKT_SIZE); ep93xx_start_hw()
625 wrl(ep, REG_RXCTL, REG_RXCTL_DEFAULT); ep93xx_start_hw()
626 wrl(ep, REG_TXCTL, REG_TXCTL_ENABLE); ep93xx_start_hw()
636 wrl(ep, REG_SELFCTL, REG_SELFCTL_RESET); ep93xx_stop_hw()
678 wrl(ep, REG_GIINTMSK, REG_GIINTMSK_ENABLE); ep93xx_open()
692 wrl(ep, REG_GIINTMSK, 0); ep93xx_close()
|
| /linux-4.1.27/drivers/net/ethernet/marvell/ |
| H A D | pxa168_eth.c | 292 static inline void wrl(struct pxa168_eth_private *pep, int offset, u32 data) wrl() function
303 wrl(pep, SDMA_CMD, SDMA_CMD_AR | SDMA_CMD_AT); abort_dma()
571 wrl(pep, HTPR, pep->htpr_dma); init_hash_table()
586 wrl(pep, PORT_CONFIG, val); pxa168_eth_set_rx_mode()
632 wrl(pep, MAC_ADDR_HIGH, mac_h); pxa168_eth_set_mac_address()
633 wrl(pep, MAC_ADDR_LOW, mac_l); pxa168_eth_set_mac_address()
651 wrl(pep, ETH_C_TX_DESC_1, eth_port_start()
656 wrl(pep, ETH_C_RX_DESC_0, eth_port_start()
659 wrl(pep, ETH_F_RX_DESC_0, eth_port_start()
663 wrl(pep, INT_CAUSE, 0); eth_port_start()
666 wrl(pep, INT_MASK, ALL_INTS); eth_port_start()
670 wrl(pep, PORT_CONFIG, val); eth_port_start()
675 wrl(pep, SDMA_CMD, val); eth_port_start()
684 wrl(pep, INT_MASK, 0); eth_port_reset()
687 wrl(pep, INT_CAUSE, 0); eth_port_reset()
701 wrl(pep, PORT_CONFIG, val); eth_port_reset()
864 wrl(pep, INT_CAUSE, ~icr); pxa168_eth_collect_events()
882 wrl(pep, INT_MASK, 0); pxa168_eth_int_handler()
931 wrl(pep, PORT_CONFIG_EXT, set_port_config_ext()
966 wrl(pep, PORT_CONFIG, cfg); pxa168_eth_adjust_link()
967 wrl(pep, PORT_CONFIG_EXT, cfgext); pxa168_eth_adjust_link()
1011 wrl(pep, INT_MASK, 0); pxa168_init_hw()
1012 wrl(pep, INT_CAUSE, 0); pxa168_init_hw()
1014 wrl(pep, INT_W_CLEAR, 0); pxa168_init_hw()
1024 wrl(pep, SDMA_CONFIG, SDCR_BSZ8 | /* Burst size = 32 bytes */ pxa168_init_hw()
1030 wrl(pep, PORT_CONFIG, PCR_HS); /* Hash size is 1/2kb */ pxa168_init_hw()
1192 wrl(pep, INT_MASK, 0); pxa168_eth_stop()
1193 wrl(pep, INT_CAUSE, 0); pxa168_eth_stop()
1195 wrl(pep, INT_W_CLEAR, 0); pxa168_eth_stop()
1267 wrl(pep, INT_MASK, ALL_INTS); pxa168_rx_poll()
1294 wrl(pep, SDMA_CMD, SDMA_CMD_TXDH | SDMA_CMD_ERD); pxa168_eth_start_xmit()
1331 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | SMI_OP_R); pxa168_smi_read()
1355 wrl(pep, SMI, (phy_addr << 16) | (regnum << 21) | pxa168_smi_write()
|
| H A D | mv643xx_eth.c | 444 static inline void wrl(struct mv643xx_eth_private *mp, int offset, u32 data) wrl() function
1816 wrl(mp, off, v); mv643xx_eth_program_unicast_filter()
1856 wrl(mp, SPECIAL_MCAST_TABLE(port_num) + i, accept); mv643xx_eth_program_multicast_filter()
1857 wrl(mp, OTHER_MCAST_TABLE(port_num) + i, accept); mv643xx_eth_program_multicast_filter()
1887 wrl(mp, SPECIAL_MCAST_TABLE(mp->port_num) + i, mc_spec[i >> 2]);
1888 wrl(mp, OTHER_MCAST_TABLE(mp->port_num) + i, mc_other[i >> 2]);
2893 wrl(mp, PHY_ADDR, data); phy_addr_set()
3165 wrl(mp, WINDOW_PROTECT(mp->port_num), mp->shared->win_protect); mv643xx_eth_probe()
|