Searched refs:vram_width (Results 1 – 18 of 18) sorted by relevance
98 rdev->mc.vram_width = 128; in r520_vram_get_type()103 rdev->mc.vram_width = 32; in r520_vram_get_type()106 rdev->mc.vram_width = 64; in r520_vram_get_type()109 rdev->mc.vram_width = 128; in r520_vram_get_type()112 rdev->mc.vram_width = 256; in r520_vram_get_type()115 rdev->mc.vram_width = 128; in r520_vram_get_type()119 rdev->mc.vram_width *= 2; in r520_vram_get_type()
458 case 0: rdev->mc.vram_width = 64; break; in r300_mc_init()459 case 1: rdev->mc.vram_width = 128; break; in r300_mc_init()460 case 2: rdev->mc.vram_width = 256; break; in r300_mc_init()461 default: rdev->mc.vram_width = 128; break; in r300_mc_init()
2715 rdev->mc.vram_width = 32; in r100_vram_get_type()2717 rdev->mc.vram_width = 64; in r100_vram_get_type()2720 rdev->mc.vram_width /= 4; in r100_vram_get_type()2726 rdev->mc.vram_width = 128; in r100_vram_get_type()2728 rdev->mc.vram_width = 64; in r100_vram_get_type()2732 rdev->mc.vram_width = 128; in r100_vram_get_type()3256 temp = (rdev->mc.vram_width / 8) * (rdev->mc.vram_is_ddr ? 2 : 1); in r100_bandwidth_update()3393 if (rdev->mc.vram_width == 128) in r100_bandwidth_update()3403 if (rdev->mc.vram_width == 32) { in r100_bandwidth_update()3571 temp = (rdev->mc.vram_width * rdev->mc.vram_is_ddr + 1)/128; in r100_bandwidth_update()
182 rdev->mc.vram_width = 128; in rv515_vram_get_type()187 rdev->mc.vram_width = 64; in rv515_vram_get_type()190 rdev->mc.vram_width = 128; in rv515_vram_get_type()193 rdev->mc.vram_width = 128; in rv515_vram_get_type()
271 rdev->mc.vram_width = 128; in rs400_mc_init()
453 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S'); in radeon_bo_init()
616 if (rdev->mc.vram_width == 64) { in radeon_legacy_set_clock_gating()
871 rdev->mc.vram_width = 128; in rs600_mc_init()
157 rdev->mc.vram_width = 128; in rs690_mc_init()
1670 rdev->mc.vram_width = numchan * chansize; in rv770_mc_init()
687 unsigned vram_width; member
1412 rdev->mc.vram_width = numchan * chansize; in r600_mc_init()
3786 rdev->mc.vram_width = numchan * chansize; in evergreen_mc_init()
4241 rdev->mc.vram_width = numchan * chansize; in si_mc_init()
5758 rdev->mc.vram_width = numchan * chansize; in cik_mc_init()
2057 case 0: rinfo->vram_width = 64; break; in radeon_identify_vram()2058 case 1: rinfo->vram_width = 128; break; in radeon_identify_vram()2059 case 2: rinfo->vram_width = 256; break; in radeon_identify_vram()2060 default: rinfo->vram_width = 128; break; in radeon_identify_vram()2066 rinfo->vram_width = 32; in radeon_identify_vram()2068 rinfo->vram_width = 64; in radeon_identify_vram()2071 rinfo->vram_width = 128; in radeon_identify_vram()2073 rinfo->vram_width = 64; in radeon_identify_vram()2084 rinfo->vram_width); in radeon_identify_vram()
321 int vram_width; member
420 if (rinfo->vram_width == 64) { in radeon_pm_enable_dynamic_mode()