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Searched refs:vmw_write (Results 1 – 8 of 8) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/vmwgfx/
Dvmwgfx_ldu.c112 vmw_write(dev_priv, SVGA_REG_NUM_GUEST_DISPLAYS, in vmw_ldu_commit_list()
119 vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, i); in vmw_ldu_commit_list()
120 vmw_write(dev_priv, SVGA_REG_DISPLAY_IS_PRIMARY, !i); in vmw_ldu_commit_list()
121 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_X, crtc->x); in vmw_ldu_commit_list()
122 vmw_write(dev_priv, SVGA_REG_DISPLAY_POSITION_Y, crtc->y); in vmw_ldu_commit_list()
123 vmw_write(dev_priv, SVGA_REG_DISPLAY_WIDTH, crtc->mode.hdisplay); in vmw_ldu_commit_list()
124 vmw_write(dev_priv, SVGA_REG_DISPLAY_HEIGHT, crtc->mode.vdisplay); in vmw_ldu_commit_list()
125 vmw_write(dev_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID); in vmw_ldu_commit_list()
Dvmwgfx_fifo.c48 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D); in vmw_fifo_have_3d()
126 vmw_write(dev_priv, SVGA_REG_ENABLE, 1); in vmw_fifo_init()
144 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1); in vmw_fifo_init()
174 vmw_write(dev_priv, SVGA_REG_SYNC, reason); in vmw_fifo_ping_host()
183 vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC); in vmw_fifo_release()
189 vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, in vmw_fifo_release()
191 vmw_write(dev_priv, SVGA_REG_ENABLE, in vmw_fifo_release()
193 vmw_write(dev_priv, SVGA_REG_TRACES, in vmw_fifo_release()
274 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_fifo_wait()
297 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_fifo_wait()
Dvmwgfx_irq.c190 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_seqno_waiter_add()
204 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_seqno_waiter_remove()
221 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_goal_waiter_add()
235 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask); in vmw_goal_waiter_remove()
313 vmw_write(dev_priv, SVGA_REG_IRQMASK, 0); in vmw_irq_uninstall()
Dvmwgfx_fb.c175 vmw_write(vmw_priv, SVGA_REG_NUM_GUEST_DISPLAYS, 1); in vmw_fb_set_par()
176 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, 0); in vmw_fb_set_par()
177 vmw_write(vmw_priv, SVGA_REG_DISPLAY_IS_PRIMARY, true); in vmw_fb_set_par()
178 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_X, info->var.xoffset); in vmw_fb_set_par()
179 vmw_write(vmw_priv, SVGA_REG_DISPLAY_POSITION_Y, info->var.yoffset); in vmw_fb_set_par()
180 vmw_write(vmw_priv, SVGA_REG_DISPLAY_WIDTH, info->var.xres); in vmw_fb_set_par()
181 vmw_write(vmw_priv, SVGA_REG_DISPLAY_HEIGHT, info->var.yres); in vmw_fb_set_par()
182 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID); in vmw_fb_set_par()
Dvmwgfx_kms.c1543 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, pitch); in vmw_kms_write_svga()
1546 vmw_write(vmw_priv, SVGA_REG_WIDTH, width); in vmw_kms_write_svga()
1547 vmw_write(vmw_priv, SVGA_REG_HEIGHT, height); in vmw_kms_write_svga()
1548 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, bpp); in vmw_kms_write_svga()
1585 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, i); in vmw_kms_save_vga()
1591 vmw_write(vmw_priv, SVGA_REG_DISPLAY_ID, SVGA_ID_INVALID); in vmw_kms_save_vga()
1613 vmw_write(vmw_priv, SVGA_REG_WIDTH, vmw_priv->vga_width); in vmw_kms_restore_vga()
1614 vmw_write(vmw_priv, SVGA_REG_HEIGHT, vmw_priv->vga_height); in vmw_kms_restore_vga()
1615 vmw_write(vmw_priv, SVGA_REG_BITS_PER_PIXEL, vmw_priv->vga_bpp); in vmw_kms_restore_vga()
1617 vmw_write(vmw_priv, SVGA_REG_PITCHLOCK, in vmw_kms_restore_vga()
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Dvmwgfx_drv.c410 vmw_write(dev_priv, SVGA_REG_ENABLE, in vmw_3d_resource_inc()
436 vmw_write(dev_priv, SVGA_REG_ENABLE, in vmw_3d_resource_dec()
627 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); in vmw_driver_load()
1157 vmw_write(dev_priv, SVGA_REG_TRACES, 0); in vmw_master_set()
1191 vmw_write(dev_priv, SVGA_REG_TRACES, 1); in vmw_master_set()
1226 vmw_write(dev_priv, SVGA_REG_TRACES, 1); in vmw_master_drop()
1359 vmw_write(dev_priv, SVGA_REG_ID, SVGA_ID_2); in vmw_pm_complete()
Dvmwgfx_ioctl.c140 vmw_write(dev_priv, SVGA_REG_DEV_CAP, i); in vmw_fill_compat_cap()
196 vmw_write(dev_priv, SVGA_REG_DEV_CAP, i); in vmw_get_cap_3d_ioctl()
Dvmwgfx_drv.h565 static inline void vmw_write(struct vmw_private *dev_priv, in vmw_write() function