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Searched refs:vlv_punit_read (Results 1 – 8 of 8) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
Dintel_runtime_pm.c480 ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state) in vlv_set_power_well()
485 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL); in vlv_set_power_well()
493 vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL)); in vlv_set_power_well()
533 state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask; in vlv_power_well_enabled()
547 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask; in vlv_power_well_enabled()
705 state = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe); in chv_pipe_power_well_enabled()
717 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSC_MASK(pipe); in chv_pipe_power_well_enabled()
738 ((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & DP_SSS_MASK(pipe)) == state) in chv_set_pipe_power_well()
743 ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in chv_set_pipe_power_well()
751 vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ)); in chv_set_pipe_power_well()
Dintel_sideband.c78 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr) in vlv_punit_read() function
Dintel_pm.c272 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); in chv_set_memory_dvfs()
281 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & in chv_set_memory_dvfs()
294 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in chv_set_memory_pm5()
4050 if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) in vlv_set_rps_idle()
4613 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); in cherryview_rps_max_freq()
4634 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); in cherryview_rps_max_freq()
4645 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); in cherryview_rps_rpe_freq()
4657 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); in cherryview_rps_guar_freq()
4661 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); in cherryview_rps_guar_freq()
4674 val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); in cherryview_rps_min_freq()
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Di915_sysfs.c318 freq = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); in gt_act_freq_mhz_show()
Di915_drv.h3145 u32 vlv_punit_read(struct drm_i915_private *dev_priv, u32 addr);
Dintel_display.c5045 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in valleyview_set_cdclk()
5049 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & in valleyview_set_cdclk()
5120 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); in cherryview_set_cdclk()
5124 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ) & in cherryview_set_cdclk()
Di915_irq.c1002 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP); in vlv_c0_read()
Di915_debugfs.c1210 freq_sts = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); in i915_frequency_info()