| H A D | synclink.c | 608 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0xc0 + (b)) )
611 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0xff00) + 0x80 + (b)) )
614 usc_OutReg( (a), ICR, (u16)((usc_InReg((a),ICR) & 0x0f00) + 0xb000) )
617 usc_OutReg( (a), ICR, (u16)(usc_InReg((a),ICR) & 0x7f00) )
646 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) | (b)) )
649 usc_OutReg( (a), SICR, (u16)(usc_InReg((a),SICR) & ~(b)) )
661 usc_OutReg( (a), TMR, (u16)((usc_InReg((a),TMR) & 0xfffc) | (b)) )
663 usc_OutReg( (a), RMR, (u16)((usc_InReg((a),RMR) & 0xfffc) | (b)) )
669 static u16 usc_InReg( struct mgsl_struct *info, u16 Port );
1162 u16 status = usc_InReg( info, RCSR ); mgsl_isr_receive_status()
1181 (usc_InReg(info, RICR) & ~RXSTATUS_ABORT_RECEIVED)); mgsl_isr_receive_status()
1214 u16 status = usc_InReg( info, TCSR ); mgsl_isr_transmit_status()
1282 u16 status = usc_InReg( info, MISR ); mgsl_isr_io_pin()
1387 (unsigned short)(usc_InReg(info,SICR) & ~(SICR_TXC_ACTIVE+SICR_TXC_INACTIVE)) ); mgsl_isr_io_pin()
1452 usc_OutReg( info, RICR+LSBONLY, (u16)(usc_InReg(info, RICR+LSBONLY) & ~BIT3 )); mgsl_isr_receive_data()
1456 while( (Fifocount = (usc_InReg(info,RICR) >> 8)) ) { mgsl_isr_receive_data()
1465 status = usc_InReg(info, RCSR); mgsl_isr_receive_data()
1535 u16 status = usc_InReg( info, MISR ); mgsl_isr_misc()
1694 UscVector = usc_InReg(info, IVR) >> 9; mgsl_interrupt()
1842 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) | BIT14)); shutdown()
1847 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) | BIT12)); shutdown()
2707 u16 oldreg = usc_InReg(info,RICR); mgsl_wait_event()
2775 usc_OutReg(info, RICR, usc_InReg(info,RICR) & mgsl_wait_event()
2911 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) | BIT7)); mgsl_break()
2913 usc_OutReg(info,IOCR,(u16)(usc_InReg(info,IOCR) & ~BIT7)); mgsl_break()
3172 while (!(usc_InReg(info,TCSR) & TXSTATUS_ALL_SENT) && mgsl_wait_until_sent()
3530 u16 Tcsr = usc_InReg( info, TCSR ); line_info()
3532 u16 Ticr = usc_InReg( info, TICR ); line_info()
3533 u16 Rscr = usc_InReg( info, RCSR ); line_info()
3535 u16 Ricr = usc_InReg( info, RICR ); line_info()
3536 u16 Icr = usc_InReg( info, ICR ); line_info()
3537 u16 Dccr = usc_InReg( info, DCCR ); line_info()
3538 u16 Tmr = usc_InReg( info, TMR ); line_info()
3539 u16 Tccr = usc_InReg( info, TCCR ); line_info()
4613 * usc_InReg()
4626 static u16 usc_InReg( struct mgsl_struct *info, u16 RegAddr ) usc_InReg() function
4631 } /* end of usc_InReg() */
4655 RegValue=usc_InReg(info,TMDR); usc_set_sdlc_mode()
4696 (unsigned short)((usc_InReg(info, IOCR) & ~(BIT13|BIT12)) | BIT12)); usc_set_sdlc_mode()
4805 RegValue = usc_InReg( info, RICR ) & 0xc0; usc_set_sdlc_mode()
5048 (u16)(usc_InReg(info,SICR) | SICR_CTS_INACTIVE) ); usc_set_sdlc_mode()
5059 usc_OutReg(info, SICR, (u16)(usc_InReg(info,SICR) | BIT3)); usc_set_sdlc_mode()
5071 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT15) & ~BIT14)); usc_set_sdlc_mode()
5220 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) | (BIT7 | BIT6)); usc_enable_loopback()
5249 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); usc_enable_loopback()
5252 usc_OutReg(info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004)); usc_enable_loopback()
5259 usc_OutReg(info,IOCR,usc_InReg(info,IOCR) & ~(BIT7 | BIT6)); usc_enable_loopback()
5312 usc_OutReg( info, HCR, (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); usc_enable_aux_clock()
5315 usc_OutReg( info, IOCR, (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) ); usc_enable_aux_clock()
5318 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); usc_enable_aux_clock()
5438 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); usc_process_rxoverrun_sync()
5463 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); usc_process_rxoverrun_sync()
5493 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); usc_stop_receiver()
5520 usc_OutReg( info, CCSR, (u16)(usc_InReg(info,CCSR) | BIT13) ); usc_start_receiver()
5721 while( (Fifocount = usc_InReg(info, TICR) >> 8) && info->xmit_cnt ) { usc_load_txfifo()
6053 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12)); usc_set_async_mode()
6128 if (usc_InReg( info, RCSR ) & (BIT8 | BIT4 | BIT3 | BIT1)) usc_loopback_frame()
6153 usc_OutReg(info, PCR, (u16)((usc_InReg(info, PCR) | BIT13) & ~BIT12)); usc_set_sync_mode()
6241 status = usc_InReg( info, MISR ); usc_get_serial_signals()
6274 Control = usc_InReg( info, PCR ); usc_set_serial_signals()
6338 (u16)((usc_InReg( info, HCR ) & ~BIT1) | BIT0) ); usc_enable_async_clock()
6344 (u16)((usc_InReg(info, IOCR) & 0xfff8) | 0x0004) ); usc_enable_async_clock()
6347 usc_OutReg( info, HCR, (u16)(usc_InReg( info, HCR ) & ~BIT0) ); usc_enable_async_clock()
6975 if ( (usc_InReg( info, SICR ) != 0) || mgsl_register_test()
6976 (usc_InReg( info, IVR ) != 0) || mgsl_register_test()
6993 if ( (usc_InReg( info, TC0R ) != BitPatterns[i]) || mgsl_register_test()
6994 (usc_InReg( info, TC1R ) != BitPatterns[(i+1)%Patterncount]) || mgsl_register_test()
6995 (usc_InReg( info, TCLR ) != BitPatterns[(i+2)%Patterncount]) || mgsl_register_test()
6996 (usc_InReg( info, RCLR ) != BitPatterns[(i+3)%Patterncount]) || mgsl_register_test()
6997 (usc_InReg( info, RSR ) != BitPatterns[(i+4)%Patterncount]) || mgsl_register_test()
7036 usc_OutReg( info, PCR, (unsigned short)((usc_InReg(info, PCR) | BIT13) & ~BIT12) ); mgsl_irq_test()
7175 usc_OutReg( info, RMR, (unsigned short)((usc_InReg(info, RMR) & 0xfffc) | 0x0002) ); mgsl_dma_test()
7226 usc_OutReg( info, TCSR, (unsigned short)(( usc_InReg(info, TCSR) & 0x0f00) | 0xfa) ); mgsl_dma_test()
7250 FifoLevel = usc_InReg(info, TICR) >> 8; mgsl_dma_test()
7273 usc_OutReg( info, TMR, (unsigned short)((usc_InReg(info, TMR) & 0xfffc) | 0x0002) ); mgsl_dma_test()
7288 status = usc_InReg( info, TCSR ); mgsl_dma_test()
7298 status = usc_InReg( info, TCSR ); mgsl_dma_test()
7630 (usc_InReg( info, RICR ) | RXSTATUS_ABORT_RECEIVED ) ); usc_loopmode_insert_request()
7641 return usc_InReg( info, CCSR ) & BIT7 ? 1 : 0 ; usc_loopmode_active()
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