Searched refs:transcoder (Results 1 - 15 of 15) sorted by relevance

/linux-4.1.27/drivers/gpu/drm/i915/
H A Dintel_fifo_underrun.c48 * The code also supports underrun detection on the PCH transcoder.
192 enum transcoder pch_transcoder, ibx_set_fifo_underrun_reporting()
206 enum transcoder pch_transcoder, cpt_set_fifo_underrun_reporting()
224 DRM_ERROR("uncleared pch fifo underrun on pch transcoder %c\n", cpt_set_fifo_underrun_reporting()
288 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
292 * PCH transcoder. Notice that on some PCHs (e.g. CPT/PPT), disabling FIFO
293 * underrun reporting for one transcoder may also disable all the other PCH
300 enum transcoder pch_transcoder, intel_set_pch_fifo_underrun_reporting()
309 * NOTE: Pre-LPT has a fixed cpu pipe -> pch transcoder mapping, but LPT intel_set_pch_fifo_underrun_reporting()
310 * has only one pch transcoder A that all pipes can use. To avoid racy intel_set_pch_fifo_underrun_reporting()
311 * pch transcoder -> pipe lookups from interrupt code simply store the intel_set_pch_fifo_underrun_reporting()
364 * @pch_transcoder: the PCH transcoder (same as pipe on IVB and older)
371 enum transcoder pch_transcoder) intel_pch_fifo_underrun_irq_handler()
375 DRM_ERROR("PCH transcoder %c FIFO underrun\n", intel_pch_fifo_underrun_irq_handler()
H A Dintel_display.c977 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv, intel_pipe_to_cpu_transcoder()
1025 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; intel_wait_for_pipe_off()
1161 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, assert_fdi_tx()
1298 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, assert_pipe()
1435 "transcoder assertion failed, should be off on pipe %c but is still active\n", assert_pch_transcoder_disabled()
1515 "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n", assert_pch_dp_disabled()
1520 "IBX PCH dp port still using transcoder B\n"); assert_pch_dp_disabled()
1528 "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n", assert_pch_hdmi_disabled()
1533 "IBX PCH hdmi port still using transcoder B\n"); assert_pch_hdmi_disabled()
1549 "PCH VGA enabled on transcoder %c, should be disabled\n", assert_pch_ports_disabled()
1555 "PCH LVDS enabled on transcoder %c, should be disabled\n", assert_pch_ports_disabled()
1875 * The PCH PLL needs to be enabled before the PCH transcoder, since it
1876 * drives the transcoder clock.
1964 * pch transcoder. */ ironlake_enable_pch_transcoder()
1977 * make the BPC in transcoder be consistent with ironlake_enable_pch_transcoder()
1996 DRM_ERROR("failed to enable transcoder %c\n", pipe_name(pipe)); ironlake_enable_pch_transcoder()
2000 enum transcoder cpu_transcoder) lpt_enable_pch_transcoder()
2027 DRM_ERROR("Failed to enable PCH transcoder\n"); lpt_enable_pch_transcoder()
2036 /* FDI relies on the transcoder */ ironlake_disable_pch_transcoder()
2047 /* wait for PCH transcoder off, transcoder state */ ironlake_disable_pch_transcoder()
2049 DRM_ERROR("failed to disable transcoder %c\n", pipe_name(pipe)); ironlake_disable_pch_transcoder()
2067 /* wait for PCH transcoder off, transcoder state */ lpt_disable_pch_transcoder()
2069 DRM_ERROR("Failed to disable PCH transcoder\n"); lpt_disable_pch_transcoder()
2089 enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, intel_enable_pipe()
2149 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; intel_disable_pipe()
3914 enum transcoder cpu_transcoder = crtc->config->cpu_transcoder; ironlake_pch_transcoder_set_timings()
3981 * - update transcoder timings
3983 * - transcoder
4022 * transcoder, and we actually should do this to not upset any PCH ironlake_pch_enable()
4023 * transcoder that already use the clock when we share it. ironlake_pch_enable()
4030 /* set transcoder timing, panel must allow it */ ironlake_pch_enable()
4078 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; lpt_pch_enable()
4084 /* Set transcoder timing. */ lpt_pch_enable()
4807 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; haswell_crtc_disable()
4945 enum transcoder transcoder; get_crtc_power_domains() local
4947 transcoder = intel_pipe_to_cpu_transcoder(dev->dev_private, pipe); get_crtc_power_domains()
4950 mask |= BIT(POWER_DOMAIN_TRANSCODER(transcoder)); get_crtc_power_domains()
6141 enum transcoder transcoder = crtc->config->cpu_transcoder; intel_cpu_transcoder_set_m_n() local
6144 I915_WRITE(PIPE_DATA_M1(transcoder), TU_SIZE(m_n->tu) | m_n->gmch_m); intel_cpu_transcoder_set_m_n()
6145 I915_WRITE(PIPE_DATA_N1(transcoder), m_n->gmch_n); intel_cpu_transcoder_set_m_n()
6146 I915_WRITE(PIPE_LINK_M1(transcoder), m_n->link_m); intel_cpu_transcoder_set_m_n()
6147 I915_WRITE(PIPE_LINK_N1(transcoder), m_n->link_n); intel_cpu_transcoder_set_m_n()
6154 I915_WRITE(PIPE_DATA_M2(transcoder), intel_cpu_transcoder_set_m_n()
6156 I915_WRITE(PIPE_DATA_N2(transcoder), m2_n2->gmch_n); intel_cpu_transcoder_set_m_n()
6157 I915_WRITE(PIPE_LINK_M2(transcoder), m2_n2->link_m); intel_cpu_transcoder_set_m_n()
6158 I915_WRITE(PIPE_LINK_N2(transcoder), m2_n2->link_n); intel_cpu_transcoder_set_m_n()
6593 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_set_pipe_timings()
6662 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; intel_get_pipe_timings()
7049 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; i9xx_get_pipe_config()
7630 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; haswell_set_pipeconf()
7917 enum transcoder transcoder, intel_cpu_transcoder_get_m_n()
7926 m_n->link_m = I915_READ(PIPE_LINK_M1(transcoder)); intel_cpu_transcoder_get_m_n()
7927 m_n->link_n = I915_READ(PIPE_LINK_N1(transcoder)); intel_cpu_transcoder_get_m_n()
7928 m_n->gmch_m = I915_READ(PIPE_DATA_M1(transcoder)) intel_cpu_transcoder_get_m_n()
7930 m_n->gmch_n = I915_READ(PIPE_DATA_N1(transcoder)); intel_cpu_transcoder_get_m_n()
7931 m_n->tu = ((I915_READ(PIPE_DATA_M1(transcoder)) intel_cpu_transcoder_get_m_n()
7939 m2_n2->link_m = I915_READ(PIPE_LINK_M2(transcoder)); intel_cpu_transcoder_get_m_n()
7940 m2_n2->link_n = I915_READ(PIPE_LINK_N2(transcoder)); intel_cpu_transcoder_get_m_n()
7941 m2_n2->gmch_m = I915_READ(PIPE_DATA_M2(transcoder)) intel_cpu_transcoder_get_m_n()
7943 m2_n2->gmch_n = I915_READ(PIPE_DATA_N2(transcoder)); intel_cpu_transcoder_get_m_n()
7944 m2_n2->tu = ((I915_READ(PIPE_DATA_M2(transcoder)) intel_cpu_transcoder_get_m_n()
8180 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; ironlake_get_pipe_config()
8557 * Haswell has only FDI/PCH transcoder A. It is which is connected to haswell_get_ddi_port_state()
8559 * the PCH transcoder is on. haswell_get_ddi_port_state()
8585 pipe_config->cpu_transcoder = (enum transcoder) crtc->pipe; haswell_get_pipe_config()
8593 WARN(1, "unknown pipe linked to edp transcoder\n"); haswell_get_pipe_config()
9352 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_crtc_mode_get()
9372 pipe_config.cpu_transcoder = (enum transcoder) pipe; intel_crtc_mode_get()
10667 (enum transcoder) to_intel_crtc(crtc)->pipe; intel_modeset_pipe_config()
12292 /* Make sure no transcoder isn't still depending on us. */ for_each_intel_crtc()
14468 enum transcoder cpu_transcoder;
14478 } transcoder[4]; member in struct:intel_display_error_state
14539 enum transcoder cpu_transcoder = transcoders[i];
14541 error->transcoder[i].power_domain_on =
14544 if (!error->transcoder[i].power_domain_on)
14547 error->transcoder[i].cpu_transcoder = cpu_transcoder;
14549 error->transcoder[i].conf = I915_READ(PIPECONF(cpu_transcoder));
14550 error->transcoder[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
14551 error->transcoder[i].hblank = I915_READ(HBLANK(cpu_transcoder));
14552 error->transcoder[i].hsync = I915_READ(HSYNC(cpu_transcoder));
14553 error->transcoder[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
14554 error->transcoder[i].vblank = I915_READ(VBLANK(cpu_transcoder));
14555 error->transcoder[i].vsync = I915_READ(VSYNC(cpu_transcoder));
14606 err_printf(m, "CPU transcoder: %c\n",
14607 transcoder_name(error->transcoder[i].cpu_transcoder));
14609 error->transcoder[i].power_domain_on ? "on" : "off");
14610 err_printf(m, " CONF: %08x\n", error->transcoder[i].conf);
14611 err_printf(m, " HTOTAL: %08x\n", error->transcoder[i].htotal);
14612 err_printf(m, " HBLANK: %08x\n", error->transcoder[i].hblank);
14613 err_printf(m, " HSYNC: %08x\n", error->transcoder[i].hsync);
14614 err_printf(m, " VTOTAL: %08x\n", error->transcoder[i].vtotal);
14615 err_printf(m, " VBLANK: %08x\n", error->transcoder[i].vblank);
14616 err_printf(m, " VSYNC: %08x\n", error->transcoder[i].vsync);
7916 intel_cpu_transcoder_get_m_n(struct intel_crtc *crtc, enum transcoder transcoder, struct intel_link_m_n *m_n, struct intel_link_m_n *m2_n2) intel_cpu_transcoder_get_m_n() argument
H A Dintel_audio.c43 * The disable sequences must be performed before disabling the transcoder or
45 * transcoder and port, and after completed link training.
396 * The enable sequences may only be performed after enabling the transcoder and
433 * The disable sequences must be performed before disabling the transcoder or
H A Dintel_ddi.c1241 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_ddi_set_pipe_settings()
1272 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_ddi_set_vc_payload_alloc()
1290 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_ddi_enable_transcoder_func()
1385 enum transcoder cpu_transcoder) intel_ddi_disable_transcoder_func()
1403 enum transcoder cpu_transcoder; intel_ddi_connector_get_hw_state()
1417 cpu_transcoder = (enum transcoder) pipe; intel_ddi_connector_get_hw_state()
1431 /* if the transcoder is in MST state then intel_ddi_connector_get_hw_state()
1505 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_ddi_enable_pipe_clock()
1515 enum transcoder cpu_transcoder = intel_crtc->config->cpu_transcoder; intel_ddi_disable_pipe_clock()
2088 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; intel_ddi_get_config()
H A Dintel_drv.h293 * pipe on Haswell (where we have a special eDP transcoder). */
294 enum transcoder cpu_transcoder;
814 enum transcoder pch_transcoder,
819 enum transcoder pch_transcoder);
860 enum transcoder cpu_transcoder);
946 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
H A Dintel_hdmi.c117 enum transcoder cpu_transcoder, hsw_infoframe_data_reg()
823 /* HW workaround for IBX, we need to move the port to transcoder A intel_enable_hdmi()
824 * before disabling it, so restore the transcoder select bit here. */ intel_enable_hdmi()
875 /* HW workaround for IBX, we need to move the port to transcoder A intel_disable_hdmi()
H A Dintel_dp_mst.c244 enum transcoder cpu_transcoder = pipe_config->cpu_transcoder; intel_dp_mst_enc_get_config()
H A Di915_reg.h2770 /* CPT uses bits 29:30 for pch transcoder select */
4028 * simply shifted from the pipe to the transcoder, while
4030 * to access such registers in transcoder EDP.
5564 /* transcoder */
5595 /* Per-transcoder DIP controls (PCH) */
5608 /* Per-transcoder DIP controls (VLV) */
5716 #define LPT_TRANSCONF _PCH_TRANSACONF /* lpt has only one transcoder */
6681 /* For each transcoder, we need to select the corresponding port clock */
H A Dintel_dp.c3748 /* Hardware workaround: leaving our transcoder select intel_dp_link_down()
3749 * set to transcoder B while it's off will prevent the intel_dp_link_down()
3750 * corresponding HDMI output on transcoder A. intel_dp_link_down()
3753 * transcoder select bit can only be cleared while the intel_dp_link_down()
H A Dintel_panel.c813 enum transcoder cpu_transcoder = pch_enable_backlight()
H A Dintel_sdvo.c1442 * transcoder A before disabling it. */ intel_disable_sdvo()
1483 * to transcoder A before disabling it, so restore it here. */ intel_enable_sdvo()
H A Di915_irq.c1893 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n"); ibx_irq_handler()
1905 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n"); ibx_irq_handler()
1908 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n"); ibx_irq_handler()
H A Di915_debugfs.c3520 * If we use the eDP transcoder we need to make sure that we don't hsw_trans_edp_pipe_A_crc_wa()
3546 * If we use the eDP transcoder we need to make sure that we don't hsw_undo_trans_edp_pipe_A_crc_wa()
H A Di915_drv.h118 enum transcoder { enum
/linux-4.1.27/sound/pci/hda/
H A Dpatch_hdmi.c1560 * - transcoder can change during stream playback on Haswell update_eld()

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